Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

Abstract: A method for forming a semiconductor structure includes providing a substrate, forming an upper sacrificial layer, an upper supporting layer and a hard mask layer on the substrate, forming bottom electrodes through the upper sacrificial layer, the upper supporting layer and the hard mask layer, forming at least an opening between the bottom electrodes and through the hard mask layer and the upper supporting layer to partially expose the upper sacrificial layer. A portion of at least one of the bottom electrodes exposed from the opening has a slope profile, and a lower end of the slope profile is not lower than a lower surface of the upper supporting layer. The method further includes removing the upper sacrificial layer from the opening to form a cavity, and forming a capacitor dielectric layer along the bottom electrodes and a conductive material filling the cavity.

Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of storage node pads, a supporting structure, and a capacitor structure. The storage node pads are disposed on the substrate. The supporting structure is disposed on the substrate and includes a first supporting layer and a second supporting layer from bottom to top. The capacitor structure is disposed on the substrate, and the capacitor structure includes columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer stacked from bottom to top, wherein the columnar bottom electrodes include a first columnar bottom electrode having a symmetric columnar structure and a second columnar bottom electrode having an asymmetric columnar structure, and the first columnar bottom electrode and the second columnar bottom electrode respectively include at least one horizontal extending portion along a horizontal direction.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, including a substrate, a supporting structure and a capacitor structure. The supporting structure is disposed on the substrate, and the supporting structure includes a first supporting layer and a second supporting layer. The capacitor structure is disposed on the substrate and includes a plurality of bottom electrode layers. Each of the bottom electrode layers includes two portions extended upwardly, and one of the two portions has a first thickness between the substrate and the first supporting layer, and a second thickness between the first supporting layer and the second supporting layer, and the first thickness is greater than the second thickness.

Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: A semiconductor device includes a substrate having a plurality of parallel active regions, an isolation structure in the substrate to separate the active regions, a buried word line disposed in the substrate and cutting through the isolation structure and the active regions, and a dielectric insert structure disposed in the substrate, directly under the buried word line and between end portions of adjacent two of the active regions. A bottom surface of the dielectric insert structure is lower than a bottom surface of the isolation structure.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Abstract: A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.

Abstract: The present disclosure provides a three-dimensional memory device and a method of fabricating the same, which includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangements, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.