Patents by Inventor Yu-Chi Chang

Yu-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227747
    Abstract: The present disclosure describes an exemplary etch process in a reactor that includes a shower head and an electrostatic chuck configured to receive a radio frequency (RF) power. The shower head includes a top plate and a bottom plate with one or more gas channels that receive incoming gases. The method can include (i) rotating the top plate or the bottom plate of the shower head to a first position to allow a gas to flow through the shower head; (ii) performing a surface modification cycle that includes: applying a negative direct current (DC) bias voltage to the shower head, applying an RF power signal to the wafer chuck; and (iii) performing an etching cycle that includes: removing the negative DC bias voltage from the shower head and lowering the RF power signal applied to the wafer chuck.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung-Jui Chang, Chin-Hsing Lin, Yu Lun Ke
  • Patent number: 11209736
    Abstract: A method for manufacturing a photomask is provided. The method includes: receiving a substrate having a hard mask disposed thereover; forming a patterned photoresist over the hard mask; patterning the hard mask using the patterned photoresist as a mask; and removing the patterned photoresist. The removing of the patterned photoresist includes: oxidizing organic materials over the substrate; applying an alkaline solution onto the patterned photoresist; and removing the patterned photoresist by mechanical impact. A method for cleaning a substrate and a photomask are also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsin Hsu, Hao-Ming Chang, Shao-Chi Wei, Sheng-Chang Hsu, Cheng-Ming Lin
  • Publication number: 20210343881
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.
    Type: Application
    Filed: July 8, 2021
    Publication date: November 4, 2021
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20210288090
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and having a plurality of first color filter segments. The solid-state image sensor further includes a second color filter layer disposed adjacent to the first color filter layer and having a plurality of second color filter segments. The solid-state image sensor includes a first grid structure disposed between the first color filter layer and the second color filter layer. The first grid structure has a first grid height. The solid-state image sensor also includes a second grid structure disposed between the first color filter segments and between the second color filter segments. The second grid structure has a second grid height that is lower than or equal to the first grid height.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Ching-Hua LI, Yu-Chi CHANG, Cheng-Hsuan LIN, Han-Lin WU
  • Patent number: 11063157
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20210202711
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Inventors: Hsin-Li Cheng, Liang-Tai Kuo, Yu-Chi Chang
  • Publication number: 20210202761
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 10985240
    Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10971404
    Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chi Chang, Hsin-Li Cheng, Felix Ying-Kit Tsui
  • Patent number: 10971596
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Liang-Tai Kuo, Yu-Chi Chang
  • Patent number: 10964586
    Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10931191
    Abstract: A half bridge circuit driver chip and the protection method thereof are provided. The high side voltage detecting circuit connects to a high side signal output terminal and detects the high side turn-on voltage of the high side transistor, so as to obtain a high side turn-on signal. The low side voltage detection circuit connects to a low side signal output terminal and detects a low side turn-on voltage of a low side transistor, so as to obtain a low side turn on signal. When the high side turn-on signal and the low side turn-on signal are received by a protection circuit, a reset signal is generated. The reset signal is sent to the high side driving circuit for turning off the high side transistor and to the low side driving circuit for turning off the low side transistor.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 23, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Yu-Chi Chang
  • Patent number: 10833655
    Abstract: A driver chip includes a high side input terminal, a pulse generator, a level shift, a current detector, a high side output controller, and a high side output terminal. The high side input terminal receives the high side input signal and the pulse generator transfers the high side input signal into the rise pulse signal and the fall pulse signal. The current detector detects the first current and the second current flowing through the level shift, and the high side output controller generates the high side output signal. The high side output terminal controls the switching of the high side transistor by the high side output signal.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 10, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Yu-Chi Chang
  • Patent number: 10798497
    Abstract: A hearing aid device comprising: a body, accommodating a circuit unit; a ear mold, capable of being accommodated in ear canal to convey sound; a connecting portion, capable of connecting the body with the ear mold; a wireless transmission unit, electrically coupled with the circuit unit, capable of communicating with at least one wireless device; and a rechargeable battery unit, coupled with the body and provided with a convex structure on a side facing the body.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 6, 2020
    Inventor: Tom Yu-Chi Chang
  • Publication number: 20200286987
    Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.
    Type: Application
    Filed: May 12, 2020
    Publication date: September 10, 2020
    Inventors: WEN-SHUN LO, YU-CHI CHANG, FELIX YING-KIT TSUI
  • Patent number: 10763329
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10692788
    Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shun Lo, Ching-Hsien Huang, Yu-Chi Chang
  • Patent number: 10686000
    Abstract: A solid-state imaging device includes multiple photoelectric conversion elements arrayed in a pixel array. The solid-state imaging device also includes a color filter layer having multiple color filter segments above the photoelectric conversion elements. Each of the color filter segments is disposed in a respective pixel of the pixel array. The solid-state imaging device further includes an optical waveguide layer over the color filter layer. The optical waveguide layer includes a waveguide partition grid and a waveguide material in the spaces of the waveguide partition grid. The waveguide material has a refractive index that is higher than the refractive index of the waveguide partition grid. The waveguide material provides the same refractive index for each pixel of the pixel array.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 16, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Cheng-Hsuan Lin, Zong-Ru Tu, Yu-Chi Chang, Ching-Hua Li
  • Patent number: 10658456
    Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Publication number: 20200144389
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Hsin-Li Cheng, Liang-Tai Kuo, Yu-Chi Chang