Patents by Inventor Yu-Chi Chang

Yu-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11606063
    Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 14, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chien-Wei Chen, Yu-Li Hsueh, Keng-Meng Chang, Yao-Chi Wang
  • Publication number: 20230073737
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a semiconductor substrate having photoelectric conversion elements. The solid-state image sensor also includes an isolation structure disposed between the photoelectric conversion elements. The solid-state image sensor further includes a color filter layer disposed above the semiconductor substrate and having color filter segments that correspond to the photoelectric conversion elements. Moreover, the solid-state image sensor includes an organic film disposed above the color filter layer. The solid-state image sensor also includes an upper electrode and a lower electrode respectively disposed on the upper side and the lower side of the organic film. The solid-state image sensor further includes nano-structures disposed on the upper side or the lower side of the organic film.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Ching-Hua LI, Zong-Ru TU, Yu-Chi CHANG
  • Publication number: 20230060387
    Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Patent number: 11589391
    Abstract: A communication device includes a radio transceiver and a collision detection device. The radio transceiver is configured to receive a wireless signal which includes an acknowledgment packet from a wireless communication channel. The acknowledgment packet includes acknowledgment information which corresponds to a plurality of transmitted packets. The collision detection device is coupled to the radio transceiver and configured to receive the acknowledgment packet, determine whether collision has occurred in the wireless communication channel according to the acknowledgment information corresponding to the transmitted packets and accordingly generate a detection result. The collision detection device determines whether collision has occurred according to a distribution of the acknowledgment information having a predetermined acknowledgment status.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 21, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Chi Lai, Wei-Hsuan Chang, Yu-Nan Lin
  • Publication number: 20230029820
    Abstract: An image sensor is provided. The image sensor includes a substrate, an isolation structure on the substrate, a photoelectric conversion layer, a transparent electrode layer, an encapsulation layer, a color filter layer, and a micro-lens. The isolation structure is electrically non-conductive and defines a plurality of pixel regions on the substrate. The isolation structure prevents cross-talk of electrical signals among pixels. The photoelectric conversion layer is disposed on the pixel regions defined by the isolation structure. The transparent electrode layer is disposed over the isolation structure and the photoelectric conversion layer. The encapsulation layer is disposed over the transparent electrode layer. The micro-lens is disposed on the color filter layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 2, 2023
    Inventors: Wei-Lung TSAI, Shin-Hong KUO, Huang-Jen CHEN, Yu-Chi CHANG, Ching-Chiang WU, Han-Lin WU, Hung-Jen TSAI
  • Patent number: 11566422
    Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: January 31, 2023
    Assignee: MINIWIZ CO., LTD.
    Inventors: Chian-Chi Huang, Tzu-Wei Liu, Jui-Ping Chen, Yu-Ying Yai, Yu-Tung Hsing, Pei-Yi Huang, Min-Wei Lin, Yi-Chun Chang, Ling-Hsiang Weng
  • Publication number: 20230014551
    Abstract: A method for receiving a full training data set including a plurality of individual training data set, dividing the plurality of individual training sets into N classes, where N is an integer greater than three, dividing the N classes into M full data classes and N-M partial data classes, performing training to obtain a trained fixed size machine learning (ML) classification model and a trained in-class confidence model, outputting a first set of prediction value(s) based on the performance of training, distributing each class of the N classes of individual training data sets to a different node of a distributed machine learning system; and outputting, from the nodes of the distributed machine learning system, a second set of prediction value(s) for each class of the N classes.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Inventors: CHAO-MIN CHANG, Yu-Chi Tang, Bo-Yu Kuo, Yu-Jin Chen
  • Publication number: 20230017479
    Abstract: A display panel is provided. The display panel includes a sensing region. The display panel includes a capping substrate, a light shielding layer, and a transparent material. The light shielding layer is disposed under the capping substrate. The light shielding layer includes a plurality of holes. The transparent material is disposed under the light shielding layer. The plurality of holes and the transparent material correspond to the sensing region.
    Type: Application
    Filed: June 14, 2022
    Publication date: January 19, 2023
    Inventors: Yun-Chun LIOU, Yen-Chi CHANG, Yu-Ting CHEN, Bo-Yu WU, Mei-Jie YANG
  • Publication number: 20230000315
    Abstract: A medical device includes an outer tube, an operation portion at least partially located in the outer tube and a control portion having a channel communicated with the outer tube along the first direction. The second end of the control portion is coupled with the first end of the outer tube, so that the channel and the outer tube are communicated with each other along the first direction. The control portion includes a control module including a suction control unit having a stopping unit and configured to move along a second direction which is different form the first direction, a suction port actuator located at a side opposite to the suction control unit with the channel therebetween and a switching unit configured to switch the work status of the operation portion. The suction port actuator is configured to be activated by the suction control unit.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 5, 2023
    Applicant: Clearmind Biomedical, Inc.
    Inventors: Sheng-Chi LIN, Feng-Cheng CHANG, Yu-Jen LIN
  • Patent number: 11538839
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a plurality of color filter segments. The solid-state image sensor further includes a partition grid disposed between the color filter segments. Moreover, the solid-state image sensor includes a patterned structure disposed on the color filter layer. The patterned structure has a plurality of patterned segments. The solid-state image sensor also includes a transparent layer disposed on the color filter layer and the partition grid. The transparent layer surrounds the patterned segments. At least one patterned segment is disposed on the partition grid.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: December 27, 2022
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Ching-Hua Li, Yu-Chi Chang, Zong-Ru Tu
  • Patent number: 11532550
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11532556
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11527609
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Publication number: 20220388293
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer, and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution is composed of a second hydrophilic solution.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 8, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • Publication number: 20220384416
    Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
  • Publication number: 20220375860
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate and directly contacting a bottom surface of the first source/drain feature.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 24, 2022
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11508661
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Publication number: 20220367663
    Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Publication number: 20220359388
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: D971948
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 6, 2022
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen