Patents by Inventor Yu-Chun Chang

Yu-Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11511380
    Abstract: A method for capturing a tool path, applicable to a machine tool having a controller and furnished with a tooling, includes the steps of: obtaining a data update frequency of the controller; calculating a feed rate of the controller, determining whether or not the feed rate is obtained, going to next step if positive, and going to the previous step if negative; reading G-codes of the controller to confirm the feed rate; and, based on the confirmed feed rate, recording machine coordinates transmitted from the controller for synthesizing a tool path file. The tool path file is used for simulation and analysis of machining of the machine tool. In addition, a device for capturing the tool path is also provided.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 29, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Ling Chang, Chih-Yuan Hsu, Guo-Wei Wang, Yu-An Tseng, Yung-Sheng Chang, Bei-Hua Yang, Chia-Chun Li, Shuo-Peng Liang
  • Publication number: 20220366116
    Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.
    Type: Application
    Filed: February 16, 2022
    Publication date: November 17, 2022
    Applicant: MEDIATEK INC.
    Inventors: Yu-Tung Chang, Yi-Chun Tsai, Tung-Kai Tsai, Yi-Te Chiu, Shih-Yun Lin, Hung-Ming Chu, Yi-Feng Chen
  • Patent number: 11502076
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20220354737
    Abstract: A wearable stimulation device includes a wearable member, a stimulation unit, and a driver. The stimulation unit is secured to the wearable member. The stimulation unit includes an immovable end, a stimulation end, and a power element. The power element is connected between the immovable end and the stimulation end for driving the stimulation end to reciprocate relative to the immovable end. The driver is in signal connection with the power element. The driver is configured to output a vibration signal to the power element for the stimulation end to have a stroke of between 8.8 mm and 10.8 mm, a thrust of between 5.6 N and 7.6 N and a reciprocating frequency of between 180 Hz and 220 Hz, thereby stimulating the deep muscles of the abdomen or waist of a human body without affecting the superficial muscles.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 10, 2022
    Inventors: CHICH-HAUNG YANG, YA-HUI CHANG, YU-MING CHANG, CHENG-CHUN CHENG
  • Publication number: 20220359671
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Application
    Filed: September 10, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20220352308
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
  • Publication number: 20220310499
    Abstract: A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Chia-Hung Liu, Hao-Yi Tsai
  • Publication number: 20220302300
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Meng-Chun CHANG
  • Patent number: 11440967
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 13, 2022
    Assignee: GlycoNex Inc.
    Inventors: Tong-Hsuan Chang, Mei-Chun Yang, Liahng-Yim Liu, Jerry Ting, Shu-Yen Chang, Yen-Ying Chen, Yu-Yu Lin, Shu-Lun Tang
  • Patent number: 11443675
    Abstract: A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: September 13, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Che-Chia Chang, Yi-Jung Chen, Shang-Jie Wu, Yu-Chieh Kuo, Hsien-Chun Wang, Ming-Hung Chuang, Mei-Yi Li, Sin-An Lin, Chen-Ying Chou
  • Publication number: 20220285566
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11430934
    Abstract: A light-emitting device includes: a substrate, including a first edge, a second edge, a third edge and a fourth edge; a semiconductor stack formed on the substrate, comprising a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, comprising a first pad electrode; and a second electrode formed on the second semiconductor layer, comprising a second pad electrode and a second finger electrode; wherein in a top view, the first pad electrode is adjacent to a corner of the substrate that is intersected by the first and the second edges; the second finger electrode is not parallel with the third and the first edges; and a distance between the second finger electrode and the first edge increases along a direction from an end of the second finger electrode that connects the second pad electrode toward the second edge.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 30, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Yu-Rui Lin, Chen Ou, Hsin-Ying Wang, Hui-Chun Yeh
  • Publication number: 20220269467
    Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.
    Type: Application
    Filed: January 10, 2022
    Publication date: August 25, 2022
    Applicant: QISDA CORPORATION
    Inventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
  • Publication number: 20220271161
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.
    Type: Application
    Filed: March 29, 2021
    Publication date: August 25, 2022
    Inventors: Ling-Chun Chou, Te-Chi Yen, Yu-Hung Chang, Kun-Hsien Lee, Kai-Lin Lee
  • Publication number: 20220251831
    Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Applicant: MINIWIZ CO.,LTD.
    Inventors: Chian-Chi HUANG, Tzu-Wei LIU, Jui-Ping CHEN, Yu-Ying YAI, Yu-Tung HSING, Pei-Yi HUANG, Min-Wei LIN, Yi-Chun CHANG, Ling-Hsiang WENG
  • Patent number: 11398557
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yi-Ching Chung, Jui-Chun Chang, Fu-Chun Tseng, Yu-Ping Ho
  • Publication number: 20220229109
    Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Yu-Wei TSENG, Chih-Ming CHANG, Wan-Chun FANG, Jui-Chung HSU, Chun-Hsi LI
  • Publication number: 20220223085
    Abstract: A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other.
    Type: Application
    Filed: September 8, 2021
    Publication date: July 14, 2022
    Inventors: Che-Chia CHANG, Yi-Jung CHEN, Shang-Jie WU, Yu-Chieh KUO, Hsien-Chun WANG, Ming-Hung CHUANG, Mei-Yi LI, Sin-An LIN, Chen-Ying CHOU
  • Publication number: 20220223086
    Abstract: A pixel driving device includes at least one data line and at least one driver integrated circuit. The at least one data line includes a first area and a second area on both sides. The first area and the second area are separated by the at least one data line. The at least one driver integrated circuit includes a first circuit and a second circuit. The first circuit is disposed in the first area, is configured to receive at least one first high-frequency signal so as to at least one first driving signal. The second circuit is disposed in the second area, is coupled to the first circuit and is configured to receive at least one low-frequency signal.
    Type: Application
    Filed: September 8, 2021
    Publication date: July 14, 2022
    Inventors: Che-Chia CHANG, Yi-Jung CHEN, Shang-Jie WU, Yu-Chieh KUO, Hsien-Chun WANG, Ming-Hung CHUANG, Mei-Yi LI, Chen-Ying CHOU, Sin-An LIN
  • Publication number: 20220216053
    Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng