Patents by Inventor Yu-Chun Chang
Yu-Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307231Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.Type: ApplicationFiled: June 2, 2023Publication date: September 28, 2023Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Publication number: 20230275131Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
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Patent number: 11705328Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.Type: GrantFiled: March 22, 2022Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Patent number: 11682578Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.Type: GrantFiled: April 16, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Hung Cheng, Yu-Chun Chang, Ching I Li, Ru-Liang Lee
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Patent number: 11670689Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: GrantFiled: September 10, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
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Publication number: 20230062874Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chen-Ming HUANG, Wen-Tuo HUANG, ShihKuang YANG, Yu-Chun CHANG, Shih-Hsien CHEN, Yu-Hsiang YANG, Yu-Ling HSU, Chia-Sheng LIN, Po-Wei LIU, Hung-Ling SHIH, Wei-Lin CHANG
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Patent number: 11594597Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: GrantFiled: October 25, 2019Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Publication number: 20220406652Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yu YANG, Po-Wei LIU, Yun-Chi WU, Yu-Wen TSENG, Chia-Ta HSIEH, Ping-Cheng LI, Tsung-Hua YANG, Yu-Chun CHANG
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Publication number: 20220359671Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.Type: ApplicationFiled: September 10, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
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Publication number: 20220352308Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Publication number: 20220216053Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Patent number: 11289330Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.Type: GrantFiled: July 30, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Publication number: 20220037199Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.Type: ApplicationFiled: April 16, 2021Publication date: February 3, 2022Inventors: Yu-Hung Cheng, Yu-Chun Chang, Ching I Li, Ru-Liang Lee
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Publication number: 20210126089Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Publication number: 20210098253Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.Type: ApplicationFiled: July 30, 2020Publication date: April 1, 2021Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Publication number: 20190015921Abstract: A laser wire feeding system includes a wire feeding device, a laser device, a first controller, and a second controller, and the first and second controllers are provided for sensing whether or not the wire feeding device normally conveys wires and whether or not a wire output end of the wire feeding device shifts is offset from the laser irradiation position of the laser device, and driving a motor to shift a horizontal shifting seat fixed with the wire feeding device to fine tune the wire feeding position according to the offset position.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: CHENG HSIN CHUANG, I CHIN CHOU, YU CHUN CHANG, HUA CHENG CHIANG, CHING CHIA CHEN
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Patent number: 10122898Abstract: An electronic device is provided. The electronic device includes a housing; a camera module disposed in the housing and having a lens outstanding from a surface of the housing; and a protection unit connected to the housing, wherein when the camera module is in an off-state, a top surface of the protection unit is higher than a surface of the lens, when the camera module is in an on-state, the top surface of the protection unit is lower than the surface of the lens.Type: GrantFiled: January 22, 2016Date of Patent: November 6, 2018Assignee: MEDIATEK INC.Inventors: Yu-Chun Chang, Tsu-Ming Liu
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Patent number: 9924608Abstract: A circuit board assembly includes a main board, a daughter board, a metal bracket, and a conductive gasket. The daughter board includes a circuit board and an electronic module with a plurality of pins connected to the circuit board. The metal bracket clamps at one side of the circuit board and the electronic module to shield the plurality of pins. The metal bracket has a connection part connecting the main board. The conductive gasket is disposed between the metal bracket and the plurality of pins.Type: GrantFiled: October 4, 2016Date of Patent: March 20, 2018Assignee: PEGATRON CORPORATIONInventors: Yao-Zheng Lin, Yu-Chun Chang
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Publication number: 20170202100Abstract: A circuit board assembly includes a main board, a daughter board, a metal bracket, and a conductive gasket. The daughter board includes a circuit board and an electronic module with a plurality of pins connected to the circuit board. The metal bracket clamps at one side of the circuit board and the electronic module to shield the plurality of pins. The metal bracket has a connection part connecting the main board. The conductive gasket is disposed between the metal bracket and the plurality of pins.Type: ApplicationFiled: October 4, 2016Publication date: July 13, 2017Inventors: YAO-ZHENG LIN, YU-CHUN CHANG
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Patent number: 9544052Abstract: A low cost, high reliability system for correcting aberrations in optical signals is disclosed. A foreoptic assembly, such as a telescope, receives an incoming optical signal and directs it to an active optical element, such as a fast steering mirror. The incoming optical signal is diffracted by a diffractive optical element to shape the image that is formed at a wavefront sensor, such as a quad-cell. The wavefront sensor measures a tip-tilt aberration of the incoming optical signal and the active optical element is adjusted to correct the measured aberration. An outgoing optical signal can be transmitted along substantially the same optical path as the incoming optical signal, but in the opposite direction. Thus, the aberration measured from the incoming optical signal can be automatically accounted for in the outgoing optical signal.Type: GrantFiled: March 5, 2013Date of Patent: January 10, 2017Assignee: AOptix Technologies, Inc.Inventors: Malcolm J. Northcott, J. Elon Graves, Siegfried Fleischer, Paolo Zambon, Jeffrey Tuttle, Yu Chun Chang