Patents by Inventor Yu-Chung Shen
Yu-Chung Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240345764Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.Type: ApplicationFiled: June 12, 2023Publication date: October 17, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
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Patent number: 12008239Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.Type: GrantFiled: January 9, 2023Date of Patent: June 11, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
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Publication number: 20240184449Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.Type: ApplicationFiled: January 9, 2023Publication date: June 6, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
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Publication number: 20240086109Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.Type: ApplicationFiled: October 17, 2022Publication date: March 14, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Yu-Chung Shen, Jia-Li Xu, Ping-Cheng Chen
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Patent number: 11467773Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.Type: GrantFiled: February 17, 2021Date of Patent: October 11, 2022Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Yu-Chung Shen, Nien-Hung Lin
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Publication number: 20220229592Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.Type: ApplicationFiled: February 17, 2021Publication date: July 21, 2022Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Yu-Chung Shen, Nien-Hung Lin
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Publication number: 20210357145Abstract: A data writing method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: writing first-type data into a first physical unit at a first write speed; and writing second-type data into a second physical unit at a second write speed. The first-type data is different from the second-type data, and the first write speed is different from the second write speed.Type: ApplicationFiled: July 3, 2020Publication date: November 18, 2021Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Yu-Chung Shen, Wei-Liang Huang, Chao-Kai Zhang
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Patent number: 9317418Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: June 17, 2014Date of Patent: April 19, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Publication number: 20140297936Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8837248Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: February 21, 2013Date of Patent: September 16, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8826461Abstract: A method and a system for protecting data, a storage device, and a storage device controller are provided. In the present method, when a host accesses data in the storage device, whether the host performs a play operation or a copy operation on the data is first determined. If the host performs the play operation on the data, the storage device continues to execute the play operation so as to allow the host to access the data. On the other hand, if the host performs the copy operation on the data, the storage device executes an interference procedure so as to prevent or retard the data from being copied into the host.Type: GrantFiled: November 20, 2009Date of Patent: September 2, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yu-Chung Shen, Yun-Chieh Chen
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Patent number: 8806301Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip has a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks of the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.Type: GrantFiled: November 19, 2009Date of Patent: August 12, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Patent number: 8416621Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: February 14, 2011Date of Patent: April 9, 2013Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8255656Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.Type: GrantFiled: June 24, 2010Date of Patent: August 28, 2012Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen
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Patent number: 8230162Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.Type: GrantFiled: February 12, 2010Date of Patent: July 24, 2012Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Publication number: 20120089766Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: ApplicationFiled: February 14, 2011Publication date: April 12, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Publication number: 20110145482Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.Type: ApplicationFiled: February 12, 2010Publication date: June 16, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Publication number: 20110087950Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip have a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks to the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.Type: ApplicationFiled: November 19, 2009Publication date: April 14, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Publication number: 20110067118Abstract: A method and a system for protecting data, a storage device, and a storage device controller are provided. In the present method, when a host accesses data in the storage device, whether the host performs a play operation or a copy operation on the data is first determined. If the host performs the play operation on the data, the storage device continues to execute the play operation so as to allow the host to access the data. On the other hand, if the host performs the copy operation on the data, the storage device executes an interference procedure so as to prevent or retard the data from being copied into the host.Type: ApplicationFiled: November 20, 2009Publication date: March 17, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Yu-Chung Shen, Yun-Chieh Chen
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Publication number: 20110066818Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.Type: ApplicationFiled: June 24, 2010Publication date: March 17, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen