Patents by Inventor Yu-Fang Wang

Yu-Fang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230097175
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11587875
    Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: U-Ting Chiu, Yu-Shih Wang, Chun-Cheng Chou, Yu-Fang Huang, Chun-Neng Lin, Ming-Hsi Yeh
  • Publication number: 20230024339
    Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.
    Type: Application
    Filed: February 9, 2022
    Publication date: January 26, 2023
    Inventors: Chih-Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia, Feng-Ching Chu, Meng-Han Lin, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11563012
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 24, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Publication number: 20220411590
    Abstract: A nanonetwork with controlled chirality prepared via self-assembly of triblock terpolymers, wherein each of the triblock terpolymers includes a first block, a second block and a third block. The first block is connected to the second block, and the third block is connected to the second block. The first block, the second block and the third block are incompatible. The third block has a homochiral characteristic, and a chirality of the nanonetwork with controlled chirality is determined by the homochiral characteristic.
    Type: Application
    Filed: October 14, 2021
    Publication date: December 29, 2022
    Inventors: Hsiao-Fang WANG, Po-Ting CHIU, Chih-Ying YANG, Zhi-Hong XIE, Yu-Chueh HUNG, Jing-Yu LEE, Jing-Cherng TSAI, Ishan PRASAD, Hiroshi JINNAI, Edwin L. THOMAS, Rong-Ming HO
  • Patent number: 11474242
    Abstract: A lane stripe detecting method based on a three-dimensional LIDAR is for detecting a lane stripe of a road surface around a vehicle. A data acquisition transforming step is for obtaining a plurality of vehicle scan point coordinates. The vehicle scan point coordinates are divided into a plurality of scan lines, and each of the scan lines has a plurality of scan points. A horizontal layer lane stripe judging step is judging whether each of the scan points is a horizontal stripe point or a non-horizontal stripe point according to a threshold value of each of the scan lines. At least two of the threshold values of the scan lines are different from each other. A vertical layer lane stripe judging step is for judging whether each of the horizontal stripe points is a same lane stripe point or a different lane stripe point.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 18, 2022
    Assignee: Automotive Research & Testing Center
    Inventors: Yu-Fang Wang, Yi-Shueh Tsai, Li-You Hsu
  • Publication number: 20220251324
    Abstract: Green, fast and easy evaporating organic solvent for use as a lubricant in the processing of polytetrafluoroethylene (PTFE) and expanded polytetrafluoroethylene (ePTFE) products and processes of using the solvents to fabricate the products are disclosed herein. The products can be used in the field of bio- and medical applications, such as for use in vascular grafts, cardiovascular and soft tissue patches, facial implants, surgical sutures, and endovascular prosthesis, and for any products known in the aerospace, electronics, fabrics, filtration, industrial and sealant arts.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventors: Lih-Sheng Turng, Yiyang Xu, Yu-Jyun Lin, Dong-Fang Wang
  • Publication number: 20220238502
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
  • Patent number: 11390845
    Abstract: Provided is a method for manufacturing cell-containing blocks having steps of: preparing an standardized size mold by 3D printing (three dimensional printing) using a biocompatible elastic material; injecting a thermosensitive colloid into the mold to form a thermosensitive mold; injecting a hydrogel containing cells in to the thermosensitive mold and curing the hydrogel containing cells to form the cell-containing blocks; separating the thermosensitive mold and the cell-containing blocks at a temperature higher than a solidifying point of the thermosensitive colloid. Also provided are method for assembling the cell-containing blocks in a target configuration by using an assembling mold defining the target configuration and made of a thermoreversible material.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 19, 2022
    Assignee: Asia University
    Inventors: Yu Fang Shen, Ming You Shie, Yi Wen Chen, Wei Huang Wang
  • Publication number: 20210199805
    Abstract: A method of simultaneous localization and mapping (SLAM) is provided to position a target object. Each of detected tracked objects in a surrounding environment of the target object is classified into a moving object or a static object based on data detected at different time points. The target object is then positioned without considering any of the tracked objects that are classified into a moving object.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Automotive Research & Testing Center
    Inventors: Yu-Fang WANG, Yi-Shueh TSAI
  • Patent number: 10670701
    Abstract: A dynamic road surface detecting method based on a three-dimensional sensor is provided. The three-dimensional sensor receives a plurality of laser-emitting points reflected from a road surface to generate a plurality of three-dimensional sensor scan point coordinates which is transmitted to a point cloud processing module. The point cloud processing module transforms the three-dimensional sensor scan point coordinates to a plurality of vehicle scan point coordinates according to a coordinate translation equation, and then transforms a plurality of vehicle coordinate height values of the vehicle scan point coordinates to a road surface height reference line according to a folding line fitting algorithm. An absolute difference of two scan point height values of any two adjacent scan points on each of the scan lines is analyzed to generate a discontinuous point. The point cloud processing module links the discontinuous points to form a road boundary.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Automotive Research & Testing Center
    Inventors: Yi-Shueh Tsai, Yu-Fang Wang
  • Publication number: 20200142067
    Abstract: A lane stripe detecting method based on a three-dimensional LIDAR is for detecting a lane stripe of a road surface around a vehicle. A data acquisition transforming step is for obtaining a plurality of vehicle scan point coordinates. The vehicle scan point coordinates are divided into a plurality of scan lines, and each of the scan lines has a plurality of scan points. A horizontal layer lane stripe judging step is judging whether each of the scan points is a horizontal stripe point or a non-horizontal stripe point according to a threshold value of each of the scan lines. At least two of the threshold values of the scan lines are different from each other. A vertical layer lane stripe judging step is for judging whether each of the horizontal stripe points is a same lane stripe point or a different lane stripe point.
    Type: Application
    Filed: December 3, 2018
    Publication date: May 7, 2020
    Inventors: Yu-Fang WANG, Yi-Shueh TSAI, Li-You HSU
  • Publication number: 20200057325
    Abstract: A liquid crystal display (LCD) panel adapted to alleviate the separation issue between the pixel array substrate and the opposite substrate is provided. The LCD panel includes a pixel array substrate, a first sealant pattern, a liquid crystal layer, a second sealant pattern and an opposite substrate. The pixel array substrate has an active region and a peripheral region surrounding the active region. The first sealant pattern surrounds the active region. The liquid crystal layer is located on the active region and is located inside the first sealant pattern. The second sealant pattern is located outside the first sealant pattern, and the second sealant pattern includes at least one two-dimensional extending structure. The at least one two-dimensional extending structure is located outside a sidewall corresponding to the first sealant pattern, and includes a plurality of turning structures. The opposite substrate faces the pixel array substrate.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 20, 2020
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Yu-Fang Wang, Wen-Cheng Lu, Ming-Hua Yeh
  • Publication number: 20190178989
    Abstract: A dynamic road surface detecting method based on a three-dimensional sensor is provided. The three-dimensional sensor receives a plurality of laser-emitting points reflected from a road surface to generate a plurality of three-dimensional sensor scan point coordinates which is transmitted to a point cloud processing module. The point cloud processing module transforms the three-dimensional sensor scan point coordinates to a plurality of vehicle scan point coordinates according to a coordinate translation equation, and then transforms a plurality of vehicle coordinate height values of the vehicle scan point coordinates to a road surface height reference line according to a folding line fitting algorithm. An absolute difference of two scan point height values of any two adjacent scan points on each of the scan lines is analyzed to generate a discontinuous point. The point cloud processing module links the discontinuous points to form a road boundary.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 13, 2019
    Inventors: Yi-Shueh TSAI, Yu-Fang WANG
  • Patent number: 8007987
    Abstract: A manufacturing method of asymmetric bumps is provided. First, a substrate is provided. A film layer is then formed on the substrate. Next, a complex photomask including at least one transparent region, a number of opaque regions, and a number of semi-transparent regions is provided. Each of the semi-transparent regions is disposed between two adjacent opaque regions, and at least one light-shielding pattern is randomly disposed in each of the semi-transparent regions. The film layer is then patterned with use of the complex photomask, and multiple asymmetric bumps are formed on the substrate. By using the complex photomask, manufacturing steps of the asymmetric bumps can be reduced. Besides, a manufacturing method of a pixel structure having the above-mentioned asymmetric bumps is also provided.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: August 30, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Te-Yu Chen, Chin-Lung Yeh, Yu-Fang Wang
  • Patent number: 7999902
    Abstract: A liquid crystal display panel includes a first transparent substrate, a second transparent substrate opposite to the first transparent substrate, and a sealant disposed therebetween. The first transparent substrate includes a peripheral region, and a plurality of conductive lines disposed in the peripheral region. The conductive lines include a plurality of transparent conductive lines and non-transparent conductive lines. The sealant is disposed in the peripheral region.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: August 16, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Te-Yu Chen, Chin-Lung Yeh, Yu-Fang Wang
  • Patent number: 7816194
    Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 19, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Ya-Ju Lu, Jun-Yao Huang, Ming-Chu Chen, Yu-Fang Wang, Chun-Jen Ma
  • Publication number: 20100227442
    Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.
    Type: Application
    Filed: August 20, 2009
    Publication date: September 9, 2010
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Ya-Ju Lu, Jun-Yao Huang, Ming-Chu Chen, Yu-Fang Wang, Chun-Jen Ma
  • Patent number: 7755713
    Abstract: A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.
    Type: Grant
    Filed: September 21, 2008
    Date of Patent: July 13, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Heng-Chang Lin, Yu-Fang Wang, Ming-Kang Huang, Chih-Kun Lin
  • Patent number: 7746443
    Abstract: A method of utilizing dual-layer photoresist to form black matrixes and spacers on a control circuit substrate is provided. The dual-layer photoresist includes a layer of black resin and a layer of transparent photoresist. The black resin, having an optical density greater than three, is mainly used to achieve the effect of black matrix. The transparent photoresist is mainly used to satisfy the needed cell gap between two transparent substrates.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: June 29, 2010
    Assignee: HannStar Display Corporation
    Inventors: Chih-Chieh Lan, Hung-Yi Hung, Yu-Fang Wang