Patents by Inventor Yu H. Sun

Yu H. Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934063
    Abstract: A system may have a display that includes a plurality of light sources such as light-emitting diodes. The display may be an exterior display that is routinely operated in daytime conditions where ambient light levels are very high. To increase contrast in an exterior display, the display may include a sunlight blocking element. A static sunlight blocking element may include a louver film with asymmetric light blocking portions. The system may include an ambient light sensor that is configured to determine ambient light levels. Based on the detected ambient light level, control circuitry in the system may adjust one or more adjustable components in the display. The display may include an adjustable diffuser that has at least two states with different haze levels. The display may include an adjustable tint layer that has at least two states with different transmission levels.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: March 19, 2024
    Assignee: Apple Inc.
    Inventors: Tao Zhan, Yu P Sun, Rong Liu, Yong Seok Choi, Joshua A Spechler, Jun Qi, Victor H Yin
  • Patent number: 7064570
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Grant
    Filed: September 20, 2003
    Date of Patent: June 20, 2006
    Assignee: International Business Machines, Corporation
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Publication number: 20040061519
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Application
    Filed: September 20, 2003
    Publication date: April 1, 2004
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Patent number: 6677774
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: January 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Patent number: 6586828
    Abstract: An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28′, 30′) contained within two metal layer (M6′, M7′). The bus grid is located within each of a plurality of contiguous rectangular regions (32′), which are defined by electrical contacts (12′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASIC chip.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Yu H. Sun
  • Patent number: 6584596
    Abstract: Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: June 24, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Charles S. Chiu, Yu H. Sun
  • Publication number: 20030071343
    Abstract: An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28′, 30′) contained within two metal layer (M6′, M7′). The bus grid is located within each of a plurality of contiguous rectangular regions (32′), which are defined by electrical contacts (12′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASIC chip.
    Type: Application
    Filed: October 17, 2001
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Yu H. Sun
  • Publication number: 20030061571
    Abstract: Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 27, 2003
    Inventors: Patrick H. Buffet, Charles S. Chiu, Yu H. Sun
  • Patent number: 6538314
    Abstract: A semiconductor device comprising: a global power bus having a first portion for supplying power to a first set of circuits and a second portion for supplying power to a second set of circuits; a local power bus for supplying alternative power to the second set of circuits; and wherein the total of the width of the second portion of the global power bus and of the width of the local power bus does not exceed the width of the first portion of the global power bus.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Yu H. Sun
  • Patent number: 6523150
    Abstract: Disclosed is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Charles S. Chiu, Yu H. Sun
  • Publication number: 20020196042
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Application
    Filed: June 26, 2001
    Publication date: December 26, 2002
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M.P. Pastel, Yu H. Sun