Patents by Inventor Yu-Hao Ho
Yu-Hao Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10205014Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: GrantFiled: December 13, 2016Date of Patent: February 12, 2019Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
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Patent number: 10181512Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.Type: GrantFiled: January 10, 2018Date of Patent: January 15, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
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Publication number: 20190006355Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
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Patent number: 10170468Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.Type: GrantFiled: June 28, 2017Date of Patent: January 1, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
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Publication number: 20180350799Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Hao HO, Shin-Cheng LIN, Wen-Hsin LIN, Cheng-Tsung WU
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Patent number: 10128331Abstract: A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.Type: GrantFiled: August 1, 2017Date of Patent: November 13, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
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Publication number: 20180308934Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.Type: ApplicationFiled: January 10, 2018Publication date: October 25, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
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Patent number: 10043901Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone having a surface formed in the substrate adjacent to the first well zone, a gate oxide formed on the first well zone and the second well zone of the substrate, a gate formed on the gate oxide, a channel formed in the first well zone underneath the gate oxide, an accumulation region formed in the second well zone underneath the gate oxide adjacent to the channel, wherein only a part of the accumulation region is implanted with a dopant to form an implant region therein, and an insulation region formed on the surface of the second well zone of the substrate adjacent to the accumulation region, wherein a boundary is formed between the insulation region and the accumulation region.Type: GrantFiled: October 4, 2016Date of Patent: August 7, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin
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Patent number: 10033260Abstract: A switch-mode converter includes a high-side driver, a high-side transistor, a low-side driver, a low-side transistor, a capacitor, and an active diode. The high-side driver is supplied by the bootstrap voltage of the bootstrap node and a floating reference voltage of a floating reference node, and generates the high-side output signal. The high-side transistor provides an input voltage to the floating reference node according to the high-side output signal. The low-side driver generates the low-side output signal. The low-side transistor couples the floating reference node to a ground according to the low-side output signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides the supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node.Type: GrantFiled: December 2, 2015Date of Patent: July 24, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
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Patent number: 10014408Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.Type: GrantFiled: May 30, 2017Date of Patent: July 3, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin, Cheng-Tsung Wu, Manoj Kumar
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Patent number: 9941356Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.Type: GrantFiled: April 20, 2017Date of Patent: April 10, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
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Publication number: 20180097108Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone having a surface formed in the substrate adjacent to the first well zone, a gate oxide formed on the first well zone and the second well zone of the substrate, a gate formed on the gate oxide, a channel formed in the first well zone underneath the gate oxide, an accumulation region formed in the second well zone underneath the gate oxide adjacent to the channel, wherein only a part of the accumulation region is implanted with a dopant to form an implant region therein, and an insulation region formed on the surface of the second well zone of the substrate adjacent to the accumulation region, wherein a boundary is formed between the insulation region and the accumulation region.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Wen-Hsin LIN, Yu-Hao HO, Shin-Cheng LIN
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Patent number: 9842896Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone formed in the substrate adjacent to the first well zone, a gate oxide layer formed on the first well zone and the second well zone, a gate formed on the gate oxide layer, an insulation region formed on the surface of the second well zone, a first implant region formed in the second well zone underneath the insulation region, a second implant region formed below the first implant region, and a junction formed between the first implant region and the second implant region. At least one of the first implant region and the second implant region includes at least two sub-implant regions having different implant concentrations. The sub-implant region having the higher implant concentration is adjacent to the junction.Type: GrantFiled: February 17, 2017Date of Patent: December 12, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yu-Hao Ho, Wen-Hsin Lin, Shin-Cheng Lin
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Publication number: 20170271485Abstract: A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO, Yu-Lung CHIN
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Patent number: 9768283Abstract: A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.Type: GrantFiled: March 21, 2016Date of Patent: September 19, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho, Yu-Lung Chin
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Publication number: 20170092755Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
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Publication number: 20170054369Abstract: A switch-mode converter includes a high-side driver, a high-side transistor, a low-side driver, a low-side transistor, a capacitor, and an active diode. The high-side driver is supplied by the bootstrap voltage of the bootstrap node and a floating reference voltage of a floating reference node, and generates the high-side output signal. The high-side transistor provides an input voltage to the floating reference node according to the high-side output signal. The low-side driver generates the low-side output signal. The low-side transistor couples the floating reference node to a ground according to the low-side output signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides the supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node.Type: ApplicationFiled: December 2, 2015Publication date: February 23, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yu-Lung CHIN, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
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Publication number: 20170054357Abstract: A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.Type: ApplicationFiled: December 28, 2015Publication date: February 23, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Lung CHIN, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
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Patent number: 9577506Abstract: A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.Type: GrantFiled: December 28, 2015Date of Patent: February 21, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
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Patent number: 9559200Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.Type: GrantFiled: February 24, 2016Date of Patent: January 31, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin