Patents by Inventor Yu-Hsiang Sun

Yu-Hsiang Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230092873
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a substrate having a first face and an opposing second face, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; and a first shielding member covering the first semiconductor component and a first group of the plurality of connectors, while exposing a second group of the plurality of connectors.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chanyuan LIU, Kuo-Hsien LIAO, Yu-Hsiang SUN
  • Patent number: 11315858
    Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Yu Hsiang Sun, Suresh Ramalingam, Tien-Yu Lee, Jaspreet Singh Gandhi
  • Publication number: 20150271915
    Abstract: An enhanced chip board package structure includes a chip board and a plurality of enhanced structures, which are formed in the blind openings of the non-effective region of the chip board. Each enhanced structure has an opening. The mechanical strength is reinforced by the enhanced structures without changing the whole thickness so as to overcome the problem of warping. Meanwhile, the three-dimensional stability is thus enhanced. The opening of the enhanced structure can be selectively filled with the filler such that the mechanical strength is further reinforced and the thermally conductive effect is greatly improved.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Jun-Chung Hsu, Bo-Yu Tseng, Yu-Hsiang Sun
  • Patent number: 9070793
    Abstract: The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant, and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments, with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 30, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo-Hsien Liao, Chi-Hong Chan, Jian-Cheng Chen, Chian-Her Ueng, Yu-Hsiang Sun
  • Publication number: 20150140262
    Abstract: An insulation layer structure includes an insulation layer, at least one glass fiber embedded in the insulation layer and at least one opening penetrating through the insulation layer and cutting off the glass fiber. The glass fiber projects from a sidewall of the opening such that the ratio of the length of the glass fiber projecting from the sidewall to the width of the opening is 0.2˜33%. With the glass fiber projecting from the sidewall of the opening, the sidewall of the opening has large surface roughness and the surface area to contact with the electrolyte. As a result, the crystal growth rate for the electrolyte onto the sidewall is accelerated. Therefore, the adhesion between the electroplating layer and the sidewall of the opening is increased, thereby improving the reliability and the yield rate of the product.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Yu-Hsiang SUN, Jun-Chung HSU
  • Publication number: 20120025356
    Abstract: The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant. and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments. with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.
    Type: Application
    Filed: May 24, 2011
    Publication date: February 2, 2012
    Inventors: Kuo-Hsien Liao, Chi-Hong Chan, Jian-Cheng Chen, Chian-Her Ueng, Yu-Hsiang Sun