Patents by Inventor Yu-Hsien Lin
Yu-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10398493Abstract: A heating system includes a power supply module, a regulatory module, electrically connected to the power supply module, for modulating the power supply module, and a heating module. The heating module includes a positioning device and a conductive device. The heating module is electrically connected to the power supply module and the regulatory module, and the conductive device is tightly wound around the positioning device.Type: GrantFiled: December 31, 2014Date of Patent: September 3, 2019Assignee: National Cheng Kung UniversityInventors: Sheng-Jye Hwang, Huy-Tien Bui, Yu-Hsien Lin, Yi-San Chang, Huei-Huang Lee, Durn-Yuan Huang, Xi-Zhang Lin
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Publication number: 20190252193Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
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Patent number: 10354510Abstract: A detection system for detecting a moving object crossing a border includes a sense device and a positioning device. The sense device is disposed on a moving object and has a first position module. The first position module generates a first position signal based on the sense device. The positioning device is signally connected with the sense device and has a calculating module, a second position module, a detecting module, and a warning module. The positioning device receives the first position signal. The calculating module sets a border. The second position module generates a second position signal based on the positioning device. The detecting module determines if the sense device is out of the border based on the first position signal and the second position signal. The warning module sends out a warning signal.Type: GrantFiled: October 30, 2017Date of Patent: July 16, 2019Assignee: Harbinger Technology CorporationInventors: Yuan-Tung Hung, Der-Hsin Chou, Kou-Sou Huang, Yu-Hsien Lin
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Patent number: 10325912Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: October 30, 2017Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang
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Publication number: 20190165137Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: March 1, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen CHEN, Ming-Ching CHANG, Yi-Chun CHEN, Yu-Hsien LIN, Li-Wei YIN, Tzu-Wen PAN, Cheng-Chung CHANG, Shao-Hua HSU
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Publication number: 20190131297Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: RYAN CHIA-JEN CHEN, LI-WEI YIN, TZU-WEN PAN, YI-CHUN CHEN, CHENG-CHUNG CHANG, SHAO-HUA HSU, YU-HSIEN LIN, MING-CHING CHANG
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Publication number: 20190131298Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: November 30, 2018Publication date: May 2, 2019Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20190130721Abstract: A detection system for detecting a moving object crossing a border includes a sense device and a positioning device. The sense device is disposed on a moving object and has a first position module. The first position module generates a first position signal based on the sense device. The positioning device is signally connected with the sense device and has a calculating module, a second position module, a detecting module, and a warning module. The positioning device receives the first position signal. The calculating module sets a border. The second position module generates a second position signal based on the positioning device. The detecting module determines if the sense device is out of the border based on the first position signal and the second position signal. The warning module sends out a warning signal.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Inventors: Yuan-Tung HUNG, Der-Hsin CHOU, Kou-Sou HUANG, Yu-Hsien LIN
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Patent number: 10276392Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: GrantFiled: July 6, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
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Publication number: 20190123198Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
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Publication number: 20190115262Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: December 21, 2018Publication date: April 18, 2019Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 10164093Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.Type: GrantFiled: March 13, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
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Patent number: 10163720Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.Type: GrantFiled: October 23, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 9996011Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.Type: GrantFiled: April 4, 2016Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Publication number: 20180061715Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.Type: ApplicationFiled: October 23, 2017Publication date: March 1, 2018Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
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Patent number: 9847273Abstract: A clip for fixing a heat sink on a retaining bracket includes an elastic supporter, an operating member, a movable fastener and a fixing bar. Two ends of the elastic supporter have a connecting portion and a first buckle portion, respectively. The operating member has a resisting portion, a pivot portion and an operating bar. The pivot portion pivots to the connecting portion. The movable fastener installs on the resisting portion and the connecting portion, and includes two sliding slots, a resisting surface and a second buckle portion. The resisting portion has an arc surface for resisting against the resisting surface. The distance between the apex of the arc surface and the pivot portion is the largest distance between the arc surface and the pivot portion. When the clip is locked, the junction of the resisting portion and the resisting surface excludes the apex of the arc surface.Type: GrantFiled: July 18, 2013Date of Patent: December 19, 2017Assignee: Delta Electronics, Inc.Inventors: Yu-Hsien Lin, Li-Kuang Tan
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Publication number: 20170348039Abstract: The present application relates to a heating system, which has a power supply module (11), a regulatory module, electrically connected to the power supply module (11), for modulating the power supply module (11), and a heating module (13). The heating module (13) comprises a positioning device and a conductive device. The heating module (13) is electrically connected to the power supply module (11) and the regulatory module, and the conductive device is tightly wound around the positioning device.Type: ApplicationFiled: December 31, 2014Publication date: December 7, 2017Inventors: Sheng-Jye Hwang, Huy-Tien Bui, Yu-Hsien Lin, Yi-San Chang, Huei-Huang Lee, Durn-Yuan Huang, Xi-Zhang Lin
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Patent number: 9804775Abstract: A method for managing user interface of an electronic device includes detecting touch points on a back panel of the electronic device within a predetermined time interval when the electronic device is unlocked. When a first number of the detected touch points on a left part of a back panel is more than a second number of the detected touch points on a right part of the back panel, icons are displayed on a right part of a display device of the electronic device. When a first number of the detected touch points on the left part of the back panel is less than the second number of the detected touch points on the right part of the back panel, the icons are displayed on a left part of the display device.Type: GrantFiled: May 15, 2015Date of Patent: October 31, 2017Assignee: FIH (HONG KONG) LIMITEDInventors: Yu-Hsien Lin, Hung-Ling Wei
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Publication number: 20170309718Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: ApplicationFiled: July 6, 2017Publication date: October 26, 2017Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
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Patent number: 9799567Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.Type: GrantFiled: October 23, 2014Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen