Abstract: A piezoelectronic device and a method of fabricating the same are provided. The piezoelectronic device has a plurality of carbon nanotubes; at least one piezoceramic layer covering the plurality of carbon nanotubes; and a supporting material for supporting the carbon nanotubes and disposed between the carbon nanotubes, the supporting layer being coated with at least one piezoceramic layer, wherein the plurality of carbon nanotubes is arranged in a comb-shape.

Abstract: A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step.

Abstract: A micro electric generator is disclosed, which comprises: at least one electrically conductive fiber, and at least one piezoelectric ceramic layer covering on the surface of that at least one electrically conductive fiber. When a mechanical force is applied to deform the electrically conductive fiber covered with the piezoelectric ceramic layer, electric energy is generated. Also, a method of fabricating the said micro electric generator and an electric generating device are disclosed.

Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

Abstract: An image scanner and a method for compensating image data are provided. By using both the X-axis calibration gain and the Y-axis calibration gain, the processing time period for compensating image data is reduced. In addition, no initial calibration and no warm-up calibration are required.

Abstract: The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Abstract: An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.

Abstract: The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Abstract: A method of fabricating visible light absorbed TiO2/CNT photocatalysts and photocatalytic filters is disclosed, in which the method of fabricating the photocatalysts comprises steps: (a) providing a substrate; (b) forming a plurality of carbon nanotubes on the substrate; (c) providing a titanium source and an oxygen source; and (d) forming at least one titanium dioxide layer on the carbon nanotubes. The filter of the present invention comprises: a substrate, a plurality of carbon nanotubes, and a titanium dioxide layer. The plurality of carbon nanotubes form on the surface of the substrate, one end of each carbon nanotube connects to the substrate, and the titanium dioxide layer covers the surface of the carbon nanotubes. The filter of the present invention is a visible light absorbed filtering net, the titanium dioxide layer formed on the CNTs has high uniformity and therefore the photodegradation efficiency of the filter is an improvement.

Abstract: A heat dissipation module is disclosed, including a fan and a fastening structure. The fastening structure includes housing and at least one fixing element. The fixing element is disposed on the sidewall of the housing and has a first protruding part extruding from the inner side of the sidewall. When the fan is assembled with the fastening structure, the first protruding part partially enters into at least one molding hole of the frame of the fan and the first protruding part is placed against the edge of the molding hole.

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

Abstract: A micro electric generator is disclosed, which comprises: at least one electrically conductive fiber, and at least one piezoelectric ceramic layer covering on the surface of that at least one electrically conductive fiber. When a mechanical force is applied to deform the electrically conductive fiber covered with the piezoelectric ceramic layer, electric energy is generated. Also, a method of fabricating the said micro electric generator and an electric generating device are disclosed.

Abstract: A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area.

Abstract: The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor.

Abstract: A heat dissipating module includes a fan and a heat sink. The heat sink comprises a body and at least one movable member. The body comprises a plurality of fins, at least one first slot and at least one second slot. The first and second slots are integrally formed on the body as a single piece. The movable member, rotatably or movably coupled to the first slot, comprises a pivoting portion, an operating portion, a jointing portion and at least one fixing portion. The pivoting portion is rotatably or movably received in the first slot. A first end of the operating portion connects to the pivoting portion, rotating or moving the pivoting portion. The jointing portion, at a second end of the operating portion, selectively connects to or separates from the second slot. The fixing portion protrudes from the pivoting portion, abutting and securing the fan to the heat sink.

Abstract: A piezoelectronic device and a method of fabricating the same are disclosed. The piezoelectronic device of the present invention comprises: a plurality of carbon nanotubes; at least one piezoceramic layer covering the plurality of carbon nanotubes; and a supporting material for supporting the carbon nanotubes and disposed between the carbon nanotubes, the supporting layer being coated with at least one piezoceramic layer, wherein the plurality of carbon nanotubes is arranged in a comb-shape. The piezoelectronic device of the present invention is advantageous in having excellent elasticity (durability) and excellent piezoelectronical property. The induced current obtained from the piezoelectronic device of the present invention is about 1.5 ?A or above as well as induced voltage being over 1V when the size of the piezoelectronic block is 2.5 mm×1 mm×1 mm (length×width×height).

Abstract: A piezoelectronic device and a method of fabricating the same are disclosed. The piezoelectronic device of the present invention comprises: a plurality of carbon nanotubes; at least one piezoceramic layer covering the plurality of carbon nanotubes; and a supporting material for supporting the carbon nanotubes and disposed between the carbon nanotubes, the supporting layer being coated with at least one piezoceramic layer, wherein the plurality of carbon nanotubes is arranged in a comb-shape. The piezoelectronic device of the present invention is advantageous in having excellent elasticity (durability) and excellent piezoelectronical property. The induced current obtained from the piezoelectronic device of the present invention is about 1.5 ?A or above as well as induced voltage being over 1V when the size of the piezoelectronic block is 2.5 mm×1 mm×1 mm (length×width×height).

Abstract: A method of fabricating visible light absorbed TiO2/CNT photocatalysts and photocatalytic filters is disclosed, in which the method of fabricating the photocatalysts comprises steps: (a) providing a substrate; (b) forming a plurality of carbon nanotubes on the substrate; (c) providing a titanium source and an oxygen source; and (d) forming at least one titanium dioxide layer on the carbon nanotubes. The filter of the present invention comprises: a substrate, a plurality of carbon nanotubes, and a titanium dioxide layer. The plurality of carbon nanotubes form on the surface of the substrate, one end of each carbon nanotube connects to the substrate, and the titanium dioxide layer covers the surface of the carbon nanotubes. The filter of the present invention is a visible light absorbed filtering net, the titanium dioxide layer formed on the CNTs has high uniformity and therefore the photodegradation efficiency of the filter is an improvement.