Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.

Abstract: Various implementations of visual inspector attachments for fiber connector cleaners are disclosed. The example fiber optic inspection module includes a camera to capture an image of an end-face, a light source to illuminate the end-face, and a first mirror that reflects light from the light source to the end-face and includes a fixed point that allows the first mirror to pivot. Alternatively, an example fiber optic inspection module includes a camera to capture an image of an end-face, a light source to illuminate the end-face, and a first mirror that reflects light from the light source to the end-face and the first mirror moves in an upward direction.

Abstract: A system for the transmission of optical and electrical signals has two optical connectors wherein each of the connectors have a metal ferrule electrically connected to a conductor. The system also has an adapter wherein having the connectors optically connected to each other via the adapter also electrically connects the conductor of optical connectors via the metal ferrules of the first and second optical connectors. Alternatively, a system can have first and second optical connectors wherein each of the connectors have an outer housing with a conductive interior surface. This system also has an adapter with at least one metal split sleeve wherein having the connectors optically connected to each other via the adapter also electrically connects optical connectors via the conductive interior surface of the outer housing of each optical connector contacting the at least one metal split sleeve.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: An electric transport device included an outer casing including a top, a bottom, a front, a back, and an interior space. A rear wheel assembly is mounted to the outer casing. The rear wheel assembly extends rearward of the back of the outer casing when the electric transport device is in a riding configuration. A locking mechanism is configurable in a first configuration to engage the rear wheel assembly to lock the rear wheel assembly in a riding position. The locking mechanism is configurable in a second configuration to disengage the locking mechanism from the rear wheel assembly permitting the rear wheel assembly to be moved relative to the outer casing to move the rear wheel assembly from the riding position to a stowed position.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.

Abstract: An integrated circuit includes a first inverter, a first transmission gate, and a second inverter constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A master latch is formed with the first inverter and the first clocked inverter. A slave latch is formed with the second inverter and the second clocked inverter. The first transmission gate is coupled between the master latch and the slave latch. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.

Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A touch sensing method, apparatus for a touch panel, and electronic device are provided. The method includes: determining a first number of to-sense touch sensing circuits, and determining a second number of reference touch sensing circuits, each to-sense touch sensing circuit having a corresponding reference touch sensing circuit; causing each to-sense touch sensing circuit to receive a touch excitation signal TX1, and apply TX1 to a corresponding touch sensitive cell and receive a touch sensing signal therefrom, and output a first output signal; causing each reference touch sensing circuit to receive a touch reference signal DC/TX2, and apply DC/TX2 to a corresponding touch sensitive cell and receive a reference sensing signal therefrom, wherein DC/TX2 and TX1 are different signals; and obtaining, according to respective first and second output signals, a capacitance difference of capacitances sensed by each to-sense touch sensing circuit and its corresponding reference touch sensing circuit.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

Abstract: An apparatus having a plurality of multifiber connector interfaces, where some of these multifiber connector interfaces can connect to network equipment in a network using multifiber cables, has an internal mesh implemented in two tiers. The first is configured to rearrange and the second is configured to recombine individual fiber of the different fiber groups. The light path of each transmitter and receiver is matched in order to provide proper optical connections from transmitting to receiving fibers and complex arbitrary network topologies can be implemented with at least 1/N less point to point interconnections, where N=number of channels per multifiber connector interface.

Abstract: An apparatus having a plurality of multifiber connector interfaces, where some of these multifiber connector interfaces can connect to network equipment in a network using multifiber cables, has an internal mesh implemented in two tiers. The first is configured to rearrange and the second is configured to recombine individual fiber of the different fiber groups. The light path of each transmitter and receiver is matched in order to provide proper optical connections from transmitting to receiving fibers and complex arbitrary network topologies can be implemented with at least 1/N less point to point interconnections, where N=number of channels per multifiber connector interface.

Abstract: Apparatuses having a plurality of optical duplex and parallel connector adapters, such as MPO connectors and LC adapters, where some adapters connect to network equipment in a network and others to servers or processing units such as GPUs, incorporate internal photonic circuit with a mesh. The light path of each transmitter and receivers is matched in order to provide proper optical connections from transmitting to receiving fibers, wherein complex arbitrary network topologies can be implemented.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.