Patents by Inventor Yu-Hung Cheng

Yu-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9679980
    Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, I-Ting Li, Ming-Hsiang Kao
  • Patent number: 9653574
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9634096
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Patent number: 9595589
    Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Publication number: 20160336448
    Abstract: A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: Yen-Ru LEE, Ming-Hua YU, Tze-Liang LEE, Chii-Horng LI, Pang-Yen TSAI, Lilly SU, Yi-Hung LIN, Yu-Hung CHENG
  • Patent number: 9425287
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Yi-Hung Lin, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 9412868
    Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Chii-Horng Li, Pang-Yen Tsai, Lilly Su, Yi-Hung Lin, Yu-Hung Cheng
  • Publication number: 20160163827
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Yu-Hung Cheng, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9349768
    Abstract: The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device includes a semiconductor region having a front surface and a back surface; a light-sensing region extending from the front surface towards the back surface within the semiconductor region; a gate stack formed over the semiconductor region; and at least one epitaxial passivation layer disposed at least one of over and below the light-sensing region. In some embodiments, the at least one epitaxial passivation layer includes a p-type doped silicon (Si) layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-Hsiung Tseng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Shyh-Fann Ting, Jhy-Jyi Sze, Tung-I Lin, Wei-Li Chen
  • Publication number: 20160111511
    Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Patent number: 9263339
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20160039084
    Abstract: A tool pen disclosed in the present invention includes a gathering component, a plurality of screw locking components and a first single-directional constraining mechanism. A first opening is formed on the gathering component. The screw locking components are movably disposed inside the gathering component. The screw locking component includes a body, a locking portion and a first contacting portion. The locking portion is disposed on an end of the body, and the first contacting portion is disposed on a lateral surface of the body. The first single-directional constraining mechanism includes a first slot and a first resilient component. The first slot is formed on an inner wall of the gathering component, and the first resilient component is movably disposed on the first slot. The first resilient component partly protrudes from the first slot and contacts against the first contacting portion of the screw locking component.
    Type: Application
    Filed: November 2, 2014
    Publication date: February 11, 2016
    Inventors: Yu-Che Tsai, Yu-Hung Cheng
  • Patent number: 9245974
    Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Publication number: 20150349160
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Publication number: 20150303265
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.
    Type: Application
    Filed: June 30, 2015
    Publication date: October 22, 2015
    Inventors: Yu-Hung CHENG, Cheng-Ta WU, Yeur-Luen TU, Chia-Shiung TSAI, Ru-Liang LEE, Tung-I LIN, Wei-Li CHEN
  • Patent number: 9153717
    Abstract: A method for forming a backside illuminated photo-sensitive device includes forming a gradated sacrificial buffer layer onto a sacrificial substrate, forming a uniform layer onto the gradated sacrificial buffer layer, forming a second gradated buffer layer onto the uniform layer, forming a silicon layer onto the second gradated buffer layer, bonding a device layer to the silicon layer, and removing the gradated sacrificial buffer layer and the sacrificial substrate.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Yen-Chang Chu, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20150279894
    Abstract: The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device includes a semiconductor region having a front surface and a back surface; a light-sensing region extending from the front surface towards the back surface within the semiconductor region; a gate stack formed over the semiconductor region; and at least one epitaxial passivation layer disposed at least one of over and below the light-sensing region. In some embodiments, the at least one epitaxial passivation layer includes a p-type doped silicon (Si) layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-Hsiung Tseng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Shyh-Fann Ting, Jhy-Jyi Sze, Tung-I Lin, Wei-Li Chen
  • Patent number: 9142643
    Abstract: The present disclosure provides an integrated circuit device and method for manufacturing the integrated circuit device. The disclosed method provides substantially defect free epitaxial features. An exemplary method includes forming a gate structure over the substrate; forming recesses in the substrate such that the gate structure interposes the recesses; and forming source/drain epitaxial features in the recesses. Forming the source/drain epitaxial features includes performing a selective epitaxial growth process to form an epitaxial layer in the recesses, and performing a selective etch back process to remove a dislocation area from the epitaxial layer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tsz-Mei Kwok, Chun Hsiung Tsai, Jeff J. Xu
  • Publication number: 20150263123
    Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, I-Ting Li, Ming-Hsiang Kao
  • Publication number: 20150243763
    Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen