Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714680
    Abstract: A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10707282
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. An organic layer including planarization layers and a pixel definition layer may overlap the thin-film circuitry. Thin-film encapsulation may overlap the organic layer. The thin-film encapsulation may be formed from an organic dielectric layer interposed between two layers of inorganic dielectric material. A strip of peripheral crack-stopper structures may run along an edge of the display and may surround the array of pixels. The crack-stopper structures may include parallel inorganic lines formed from a first inorganic layer such as an inorganic layer of the thin-film circuitry. A strip of the organic layer may overlap the parallel inorganic lines. The crack-stopper structures may have parallel tapered polymer lines. The polymer lines may be overlapped by a second inorganic dielectric layer formed from the inorganic material of the thin-film encapsulation layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Chih Jen Yang, Prashant Mandlik, Chia-Hao Chang, Chien-Chung Wang, Te-Hua Teng, Yu Cheng Chen
  • Publication number: 20200212298
    Abstract: A MTJ stack is deposited on a bottom electrode, the stack comprising at least a pinned layer, a barrier layer, a free layer, and a top electrode layer. The top electrode and MTJ stack are etched where not covered by a photoresist pattern to form an MTJ structure. A conformal encapsulation dielectric is deposited over the MTJ structure. A magnetic metal layer is deposited on the encapsulation dielectric and anisotropically etched leaving a magnetic metal shield on sidewalls of the MTJ structure. A dielectric layer is deposited over the magnetic metal shield and MTJ structure. The dielectric layer and encapsulation dielectric are polished away to expose the top electrode. A top metal contact layer is deposited contacting the top electrode and the magnetic metal shield wherein the magnetic metal shield has no contact with said bottom electrode and MTJ structure but is separated from them by the encapsulation dielectric.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Yi Yang, Guenole Jan, Yu-Jen Wang
  • Publication number: 20200212297
    Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Yi Yang, Vignesh Sundar, Dongna Shen, Sahil Patel, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Patent number: 10700269
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Publication number: 20200203167
    Abstract: The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.
    Type: Application
    Filed: August 30, 2019
    Publication date: June 25, 2020
    Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20200194321
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 18, 2020
    Applicant: United Microelectronics Corp.
    Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Publication number: 20200194316
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20200185454
    Abstract: A MTJ stack comprising at least a pinned layer, a barrier layer, and a free layer is deposited on a bottom electrode. A top electrode layer, a carbon-based hard mask, and a dielectric hard mask are deposited in order on the MTJ stack. First, the hard masks and MTJ stack are etched. The etched MTJ stack has a first width. During the first etching, chemical damage forms on sidewalls of the MTJ stack. Next, the carbon-based hard mask is trimmed to a second width smaller than the first width. Then in a second etching, the top electrode and free layer of said MTJ stack not covered by the trimmed carbon-based hard mask are etched to complete formation of the MTJ structure wherein during the second etching of the free layer, chemical damage is removed from the free layer and metal re-deposition is formed on sidewalls of the free layer.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10680168
    Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10670784
    Abstract: A light filter structure is provided. The light filter structure includes a first filter layer disposed over the substrate. The first filter layer has a transmittance greater than 50% in a first waveband, wherein the first filter layer is an interference-type filter. The light filter structure further includes a second filter layer disposed over the substrate. The second filter layer has a transmittance greater than 50% in a second waveband, wherein the second filter layer is an absorption-type filter. The first waveband partially overlaps the second waveband at the wavelength in a third waveband, and the third waveband is in an IR region. Furthermore, an image sensor used as a time-of-flight image sensor is also provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Wei-Ko Wang, Yu-Jen Chen, Chia-Hui Wu
  • Patent number: 10658409
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. U.
    Inventors: Sheng-Chan Li, I-Nan Chen, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 10648069
    Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >100.6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance x area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang
  • Publication number: 20200144488
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Publication number: 20200139343
    Abstract: A metal organic framework and a method for preparing the same, and an adsorption device employing the metal organic framework are provided. The metal organic framework includes a 3,5-pyridinedicarboxylic acid and a metal ion, which is an aluminum ion, a chromium ion, or a zirconium ion, wherein the 3,5-pyridinedicarboxylic acid is coordinated to the metal ion.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 7, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Chih LEE, Chang-Yi SHEN, Jiun-Jen CHEN, Yuhao KANG, Shih-Yun YEN, Yu-Xuan WANG
  • Publication number: 20200144493
    Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Dongna Shen, Yi Yang, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20200144492
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Dongna Shen, Yu-Jen Wang, Ru-Ying Tong, Vignesh Sundar, Sahil Patel
  • Publication number: 20200136030
    Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Yi Yang, Yu-Jen Wang