Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200144492
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Dongna Shen, Yu-Jen Wang, Ru-Ying Tong, Vignesh Sundar, Sahil Patel
  • Publication number: 20200136030
    Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Yi Yang, Yu-Jen Wang
  • Publication number: 20200136025
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Publication number: 20200136021
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20200135664
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20200136031
    Abstract: A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20200127192
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
  • Publication number: 20200127089
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: November 18, 2018
    Publication date: April 23, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200124967
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Publication number: 20200127195
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode in a substrate. The MTJ stack is etched to form a MTJ structure wherein portions of sidewalls of the MTJ structure are damaged by the etching. Thereafter, the substrate is removed from an etching chamber wherein sidewalls of the MTJ structure are oxidized. A physical cleaning of the MTJ structure removes damaged portions and oxidized portions of the MTJ sidewalls. Thereafter, without breaking vacuum, an encapsulation layer is deposited on the MTJ structure and bottom electrode.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Yu-Jen Wang, Keyu Pi, Ru-Ying Tong
  • Publication number: 20200119264
    Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 16, 2020
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20200115788
    Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance x area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 16, 2020
    Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang
  • Patent number: 10622047
    Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hideaki Fukuzawa, Vignesh Sundar, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 10624245
    Abstract: According to various aspects, exemplary embodiments are disclosed of laser weldable brackets for attachment of heat sinks to EMI shields, such as a board level shield, etc. In an exemplary embodiment, an assembly generally includes an electromagnetic interference (EMI) shield, a heat sink, and a bracket laser weldable to the EMI shield for attachment of the heat sink to the EMI shield. In another exemplary embodiment, a method of attaching a heat sink to an EMI generally includes laser welding a bracket to the EMI shield whereby the bracket retains the heat sink in place relative to the EMI shield.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: April 14, 2020
    Assignee: Laird Technologies, Inc.
    Inventor: Yu Jen Wang
  • Publication number: 20200110324
    Abstract: An electrically tunable focusing achromatic lens includes a first liquid crystal cell, a second liquid crystal cell, and first and second electrode layer units which have two predetermined patterns for permitting two predetermined radially varying electric fields to be generated to across the first and second liquid crystal cells, respectively, to thereby allow one of the first and second liquid crystal cells to acquire a predetermined positive optical power and the other one of the first and second liquid crystal cells to acquire a predetermined negative optical power. When an incident light passes through the first and second liquid crystal cells, chromatic aberration of the first liquid crystal cell can be counterbalanced by that of the second liquid crystal cell.
    Type: Application
    Filed: February 25, 2019
    Publication date: April 9, 2020
    Inventors: Yu-Jen WANG, Hung-Chun LIN, Yi-Hsin LIN
  • Publication number: 20200103756
    Abstract: Embodiments of the present disclosure describe a chemical replacement system and a method to automatically replace PR bottles. The chemical replacement system includes a computer system and a transfer module. The computer system can receive a request signal to replace one or more chemical containers and transmit a command to the transfer module. The transfer module, being controlled by the computer system, can include a holder configured to hold the one or more chemical containers (e.g., PR bottles); a door unit configured to open in response to the command; and a transfer unit configured to eject the holder in response to the command for replacement. The chemical replacement system can further include an automated vehicle configured to replace the one or more chemical containers in the ejected holder.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Kai CHEN, Forster Yuan, Ko-BIn Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu
  • Patent number: 10607897
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10603601
    Abstract: A party popper contains: a body which includes two first openings defined on two ends of the body respectively. A flexible push portion is mounted on an end of the body, and a launchable cylinder is slidably accommodated in the body. The body includes a surrounding rib fitted thereon, and the flexible push portion is configured to drive the launchable cylinder to slide until the launchable cylinder is stopped by the surrounding rib. Multiple launchable objects are launched from the launchable cylinder inertially, thus launching the multiple launchable objects safely.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 31, 2020
    Inventor: Yu-Jen Wang
  • Publication number: 20200096814
    Abstract: A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. Lens power control can be provided using combinations of electrode configurations, drive signals and anchoring strengths in the alignment layers.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Applicant: CooperVision International Holding Company, LP
    Inventors: Hung-Chun Lin, Yu-Jen Wang, Hao-Ren Lo, Yi-Hsin Lin
  • Publication number: 20200091419
    Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang