Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10516101
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode in a substrate. The MTJ stack is etched to form a MTJ structure wherein portions of sidewalls of the MTJ structure are damaged by the etching. Thereafter, the substrate is removed from an etching chamber wherein sidewalls of the MTJ structure are oxidized. A physical cleaning of the MTJ structure removes damaged portions and oxidized portions of the MTJ sidewalls. Thereafter, without breaking vacuum, an encapsulation layer is deposited on the MTJ structure and bottom electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Keyu Pi, Ru-Ying Tong
  • Patent number: 10516100
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
  • Publication number: 20190386201
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20190386211
    Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 19, 2019
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10510789
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20190374869
    Abstract: A party popper contains: a body which includes two first openings defined on two ends of the body respectively. A flexible push portion is mounted on an end of the body, and a launchable cylinder is slidably accommodated in the body. The body includes a surrounding rib fitted thereon, and the flexible push portion is configured to drive the launchable cylinder to slide until the launchable cylinder is stopped by the surrounding rib. Multiple launchable objects are launched from the launchable cylinder inertially, thus launching the multiple launchable objects safely.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 12, 2019
    Inventor: Yu-Jen Wang
  • Publication number: 20190363249
    Abstract: A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20190363248
    Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Dongna Shen, Yi Yang, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20190350939
    Abstract: A cancer treatment method using a Ni-SOD mimic compound is provided, which includes administrating the Ni-SOD compound to a cancer cell of a cancer. The structure of the Ni-SOD mimic compound is represented as follows: wherein R1 represents H or A-R?; A represents a bond, O or N; L represents acetonitrile, water, or t-butyl isocyanate; R? represents H, unsubstituted or substituted alkyl, polyalkoxy, polydimethylsiloxane, polyurethane or other polymer materials or amino acid groups; R2 represents unsubstituted or substituted alkyl, alkoxy, siloxy, amino, alkylamine or hydrocarbyl groups; R3 represents unsubstituted or substituted amino, alkylamine, oxyalkylamine groups or magnetic nanoparticles attached oxyalkylamine. Ni is bivalent or trivalent.
    Type: Application
    Filed: September 11, 2018
    Publication date: November 21, 2019
    Inventors: YUN-MING WANG, WAY-ZEN LEE, YU-JEN CHEN, SHOU-CHENG WU, CHIEN-WEI CHIANG
  • Publication number: 20190352063
    Abstract: A drinking vessel includes a bottle having a chamber for receiving a liquid, and a mouth communicating with the chamber of the bottle, a cover device includes a cover member for detachably attaching to the mouth, the cover member includes a port having a passage formed in the port and communicating with the chamber of the bottle, a plug is attached to a lower portion of the port and includes an orifice communicating with the passage of the port and the chamber of the bottle, a valve member is engaged in the passage of the port, and the port includes a rib for anchoring the valve member in the passage of the port and for preventing the valve member from being disengaged from the cover member.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Inventors: Hong Jen WANG, Yu Ming Wang, Kai I Wang
  • Patent number: 10483153
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Publication number: 20190348520
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Application
    Filed: June 4, 2018
    Publication date: November 14, 2019
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Publication number: 20190348601
    Abstract: A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10475709
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10475991
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness ?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10475828
    Abstract: An image sensor device structure is provided. The image sensor device structure includes a substrate, and the substrate is doped with a first conductivity type. The image sensor device structure includes a light-sensing region formed in the substrate, and the light-sensing region is doped with a second conductivity type that is different from the first conductivity type. The image sensor device structure further includes a doping region extended into the light-sensing region, and the doping region is doped with the first conductivity type. The image sensor device structure also includes a plurality of color filters formed on the doping region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Yu-Jen Wang, Shyh-Fann Ting, Wei-Chuang Wu, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20190341389
    Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20190339616
    Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Yi Yang, Dongna Shen, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10446741
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang, Jesmin Haq, Tom Zhong
  • Publication number: 20190312963
    Abstract: An internet phone system includes an internet phone main body, an expansion device and a multiple-layer connecting card. The internet phone main body includes a first connecting port. The at least one expansion device includes a second connecting port. One end of the multiple-layer connecting card is connected to the first connecting port, and the other end is connected to the second connecting port such that the internet phone main body can be electrically connected to the expansion device via the multiple-layer connecting card. The expansion device is capable of combining with another expansion device by another multiple-layer connecting card.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Yu-Ti KUO, Wen-Hsieh HSIEH, Chao-Tang CHIU, Chien-Yi LEE, Hsiao-Wen LEE, Ching-Jen WANG