Abstract: The present disclosure provides a wearable device. The wearable device includes a first sensing element configured to be disposed adjacent to a right ear of a user while the wearable device is worn by the user and a second sensing element configured to be disposed adjacent to a left ear of the user and coupled to the first sensing element while the wearable device is worn by the user. The second sensing element and the first sensing element are configured to sense a biological signal from the user. The wearable device also includes a reference electrode configured to reduce an interference to the biological signal. A headset device and a method for operating a wearable device is also provided in the present disclosure.

Abstract: A pushing force-actuated braking device includes an annular housing that houses a brake disc, a braking piston, plural braking elements, and a brake-releasing piston. When only the braking piston is under the action of a fluid, the braking piston applies an axial pushing force to the brake disc such that the brake disc is kept at a braking position jointly by the braking piston and the braking elements. When only the brake-releasing piston is under the action of a fluid, the brake-releasing piston applies an opposite pushing force to the brake disc to keep it at a brake-releasing position. Should the fluid acting on the braking piston fail, the force of the braking elements still enables the brake disc to produce a braking effect. The pushing force-actuated braking device has a modular design to facilitate assembly and disassembly. A rotary table using the braking device is also provided.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A flexure stage with modularized flexure units for convenient manufacturing, assembly and repair is provided. The flexure stage comprises a base, a platform separated from the base, and a plurality of flexure units disposed between the base and the platform. Each flexure unit comprises a first section, a second section, and a third section. The first section is located on the base. The second section is connected with the platform and separated from the first section. The third section is coupled with the first section and the second section through the first bending part and the second bending part respectively wherein the first bending part and the second bending part comprises flexibility in different axial directions.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: The present disclosure provides an ear tip. The ear tip includes a main body, a first conductive element at least partially embedded in the main body, a second conductive element at least partially embedded in the main body and spaced apart from the first conductive element. The main body includes a central portion having a top and a tail portion extending from the top of the central portion. The first conductive element is proximal to the top of the central portion and the second conductive element is distal from the top of the central portion. A wearable device is also disclosed.

Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.

Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: An electronic device for updating firmware in a target device over the air includes a dispatching module and a firmware over the air (FOTA) core. The dispatching module is configured to establish a communication link between the electronic device and the target device. The FOTA core is configured to receive information corresponding to updated firmware via the established communication link.

Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: The present disclosure provides a method for inhibiting proliferation and metastasis of cancer cells by using a naphthoquinone derivative.

Abstract: A system and method for ensuring reliable network communication for a multi-node server is disclosed. The multi-node server includes a first node having a port operable to transmit data packets. A first internal switch has a downstream port coupled to the port of the first node, an interconnection port, and uplink ports coupled to the network. The uplink ports routes data packets from the first node to the network. A second internal switch has a downstream port, an interconnection port coupled to the interconnection port of the first internal switch, and an uplink port coupled to the network. On failure of network communication at the uplink ports of the first internal switch, data packets from the first node are routed through the interconnection ports and through the uplink port of the second internal switch to the network.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: A flexure stage with modularized flexure units for convenient manufacturing, assembly and repair is provided. The flexure stage comprises a base, a platform separated from the base, and a plurality of flexure units disposed between the base and the platform. Each flexure unit comprises a first section, a second section, and a third section. The first section is located on the base. The second section is connected with the platform and separated from the first section. The third section is coupled with the first section and the second section through the first bending part and the second bending part 35 respectively wherein the first bending part and the second bending part comprises flexibility in different axial directions.