Patents by Inventor Yu-Lan Lo

Yu-Lan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200320241
    Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.
    Type: Application
    Filed: March 3, 2020
    Publication date: October 8, 2020
    Inventors: I-Hsiu Lo, Yung-Jen Chen, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 10783293
    Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 22, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shu-Yi Kao, Yu-Lan Lo, Meng-Jung Lee, Yun-Jing Lin
  • Publication number: 20200285791
    Abstract: The present invention provides a circuit design method, wherein the circuit design method includes the steps of: generating a gate-level netlist; determining at least one specific cell within a circuit according to the gate-level netlist, wherein an output signal of the at least one specific cell is always a fixed value; and replacing at least one specific cell by a tie cell to generate an updated gate-level netlist.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Inventors: I-Hsiu Lo, Wan-Ju Wu, Yung-Jen Chen, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 10657303
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Publication number: 20200151295
    Abstract: Disclosed is an IC voltage determining method including: executing a static timing analysis according to a circuit design to obtain data of a critical path and then generating a netlist; executing a circuit parameter simulation and Monte Carlo simulation with the netlist according to a regular voltage and prescribed parameters to obtain a circuit parameter reference value and a variance of circuit parameter values; executing an adaptive voltage scaling analysis according to a voltage range to obtain a voltage-versus-parameter relation indicative of the number of times that each of circuit parameter deviations that are respectively associated with predetermined voltages within the predetermined voltage range is of the variance; and testing an IC according to the regular voltage to obtain a circuit parameter test value and determining the IC voltage according to the voltage-versus-parameter relation and a difference between the circuit parameter test value and the circuit parameter reference value.
    Type: Application
    Filed: October 29, 2019
    Publication date: May 14, 2020
    Inventors: YING-CHIEH CHEN, MEI-LI YU, YU-LAN LO, HSIN-CHANG LIN, SHU-YI KAO
  • Patent number: 10521529
    Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 31, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20190384868
    Abstract: A method and apparatus for adaptive voltage scaling to eliminate delay variation of a whole design are provided. The method may include: reading a circuit simulation netlist file, a circuit design database, and a path list; building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels according to the circuit design database; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.
    Type: Application
    Filed: March 17, 2019
    Publication date: December 19, 2019
    Inventors: Mei-Li Yu, Ying-Chieh Chen, Yu-Lan Lo, Hsin-Chang Lin, Shu-Yi Kao
  • Publication number: 20190332726
    Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.
    Type: Application
    Filed: September 17, 2018
    Publication date: October 31, 2019
    Inventors: Shu-Yi KAO, Yu-Lan Lo, Meng-Jung Lee, Yun-Jing Lin
  • Publication number: 20180307782
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Patent number: 9858382
    Abstract: A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 2, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20170364619
    Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20160188782
    Abstract: A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 30, 2016
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ying-Chieh CHEN, Mei-Li YU, Ting-Hsiung WANG, Yu-Lan LO, Shu-Yi KAO
  • Patent number: 9003341
    Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20150067623
    Abstract: A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register.
    Type: Application
    Filed: August 3, 2014
    Publication date: March 5, 2015
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20140223398
    Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.
    Type: Application
    Filed: October 11, 2013
    Publication date: August 7, 2014
    Applicant: Realtek Semiconductor Corp.
    Inventors: Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 8726206
    Abstract: A deadlock detection method includes: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path. A non-transitory machine readable medium stores a program code, wherein when executed by a processor, the program code enables the processor to perform the following steps: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 13, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 8713497
    Abstract: An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added.
    Type: Grant
    Filed: January 1, 2013
    Date of Patent: April 29, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Meng-Jung Lee, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20130298095
    Abstract: A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 7, 2013
    Applicant: Realtek Semiconductor Corp.
    Inventors: Mei-Li Yu, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 8443320
    Abstract: The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: May 14, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 8166433
    Abstract: A floating net inspection method includes: providing a netlist which describes a circuit structure of an application circuit, the application circuit including a plurality of transistors; coupling a power supply port and a signal input port of the application circuit to voltage sources, respectively; generating test voltages respectively through the voltage sources, such that the test voltages are applied to the transistors, the test voltages being larger than a reference voltage; and determining whether a connecting node of one of the transistors is floating on the basis of whether a voltage of the connecting node is larger than the reference voltage.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 24, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Lan Lo