Abstract: An integrated wellhead device for filtering injected and produced gases is provided. The wellhead device comprises a horizontal tank body that is internally provided with an injected gas filtering system and a produced gas filtering system. The injected gas filtering system is internally provided with an oxygen removal chamber. A gas inlet of the injected gas filtering system is connected with an injected high-pressure gas source, and a gas outlet of the injected gas filtering system is connected with a gas injection well casing of Christmas tree. The produced gas filtering system is internally equipped with an oxygen removal chamber, a sulfur removal chamber and a carbon dioxide removal chamber. A gas inlet of the produced gas filtering system is connected with a gas production tubing of the Christmas tree, and a gas outlet of the produced gas filtering system is connected with a produced gas transmission pipe.

Abstract: A system and computer-implemented method for analysing or monitoring a subject, the method comprising: identifying one or more objects of interest that have been segmented from a first image comprising any of a baseline scan, a follow-up scan or a reference image of the subject; identifying predefined landmarks of the objects; determining reference morphometries pertaining to the objects by performing morphometrics on the objects by reference to the landmarks; selecting one or more regions of interest (ROIs) from the objects according to the reference morphometries, comprising identifying respective locations of the ROIs relative to the reference morphometries; performing a first analysis of the one or more ROIs; performing at least one corresponding second analysis of the one or more ROIs in respectively at least one second image comprising any other of a baseline scan, a follow-up scan or a reference image; and generating a comparison of one or more results of the first analysis and one or more correspondin

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.

Abstract: The invention discloses a digital imaging technology-based method for calculating relative permeability of tight core, comprising the following steps: step S1: preparing a small column sample of tight core satisfying resolution requirements; step S2: scanning the sample by MicroCT-400 and establish a digital core; step S3: performing statistical analysis on parameters reflecting the characteristics of rock pore structure and shape according to the digital core; step S4: calculating tortuosity fractal dimension DT and porosity fractal dimension Df by a 3D image fractal box dimension algorithm; step S5: performing statistical analysis on maximum pore equivalent diameter ?max and minimum pore equivalent diameter ?min by a label. The present invention solves the problems of time consumption of experiment, instrument accuracy, incapability of repeated calculation simulations and resource waste by repeated physical experiment.

Abstract: The present invention discloses a method for determining the stimulated reservoir volume of horizontal wells by coupling reservoir flow, comprising the following steps: establishing a reservoir grid based on the reservoir geological model of the target well and adding an initial fracture unit; calculating the stress intensity factor at the fracture tip, judging the fracture initiation and determining the total number of fracture units; calculating the fluid pressure of fracture units, the pore pressure distribution and water saturation distribution of the reservoir matrix and micro-fractures during hydraulic fracturing; working out the stimulated reservoir volume of the horizontal well according to the fracture parameters, pressure distribution and water saturation distribution in shale reservoirs. The present invention can simulate fracture propagation, fracturing fluid leak-off and reservoir fluid flow in the whole fracturing process, determine the stimulated reservoir volume of horizontal wells.

Abstract: A computer-implemented image analysis method and system. The method comprises: quantifying one or more features segmented and identified from a medical image of a subject; extracting clinically relevant features from non-image data pertaining to the subject; assessing the features segmented from the medical image and the features extracted from the non-image data with a trained machine learning model; and outputting one or more results of the assessing of the features.

Abstract: This invention describes packaging structures and methods for electronic devices, especially for solid electrolytic capacitor devices. A packaging structure applies at least two protective substrates to sandwich one or multiple capacitor elements stacked together in between with an insulating material surrounding the capacitor elements also in between the protective substrates. Each protective substrate comprises an anodic conductor pad and a cathodic conductor pad. The anodic conductor pad is electrically connected to an external anode terminal, which is in turn electrically connected to the tip face of the anode end of the capacitor element. The cathodic pad is electrically connected to the cathode of the capacitor element as well as to an external cathode terminal.

Abstract: An indoor positioning system, for detecting a position of a target object located in a containing body, includes a tracking label, a plurality of positioning label groups, and a scanning device. The tracking label is disposed on the target object. Each positioning label groups is disposed on the containing body and has a plurality of label units. Each label unit defines a positioning interface, which forms a plurality of areas of the containing body. The scanning device senses and reads the tracking label and each label unit of each positioning label group. The scanning device obtains the positioning interface in which the tracking label is located through an analysis computation according to a signal relationship between the tracking label and each label unit, thereby identifying the positioning interface to obtain one of the areas of the target object in the containing body.

Abstract: The invention provides novel compositions and methods for the treatment of Radiation-Induced Bystander Effects (RIBE), resulting from radiation exposure. In one preferred embodiment the inventions includes novel therapeutic agents, including but not limited to quercetin and quercetin analogs, as well as E64, CA074, CA074Me, that interfere with the activity of Cathepsin B.

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

Abstract: An inverter, a photovoltaic power generation system, and a dehumidification method. The inverter includes a ventilation valve and a pneumatic transmission device. The ventilation valve is installed on a surface of a cabinet compartment of the inverter. A controller and the pneumatic transmission device are located in the cabinet compartment. A breathable film is disposed on the ventilation valve. The pneumatic transmission device blows air in the cabinet compartment toward the breathable film when the following at least one preset condition is met. The at least one preset condition includes at least one of or more of the following cases: the inverter is running, humidity in the cabinet compartment is higher than preset humidity, and a temperature in the cabinet compartment is higher than a preset temperature.

Abstract: The present invention discloses a method for realizing uniform stimulation for the oil and gas well by low-cost multi-stage fracturing, comprising the following steps: first calculate and predict the inlet widths of the fracture created in the planned hydraulic fracturing; then design the plugging scheme for blocking the fracture inlet after each fracturing treatment; the selected plugging particles are composed of filling particles and skeleton particles, with designed plugging scheme; after complete the design of plugging scheme, perform the fracturing treatment to create hydraulic fracturing in the reservoir; skeleton particles and filling particles are added into the fractures successively according to plan. The present invention provides a multi-stage single-cluster fracturing method, with the advantages of controllable fracture sizes and low cost. The present invention can realize a good uniformity of stimulation for the oil and gas wells.

Abstract: The present invention discloses a method for realizing uniform stimulation for the oil and gas well by low-cost multi-stage fracturing, comprising the following steps: first calculate and predict the inlet widths of the fracture created in the planned hydraulic fracturing; then design the plugging scheme for blocking the fracture inlet after each fracturing treatment; the selected plugging particles are composed of filling particles and skeleton particles, with designed plugging scheme; after complete the design of plugging scheme, perform the fracturing treatment to create hydraulic fracturing in the reservoir; skeleton particles and filling particles are added into the fractures successively according to plan. The present invention provides a multi-stage single-cluster fracturing method, with the advantages of controllable fracture sizes and low cost. The present invention can realize a good uniformity of stimulation for the oil and gas wells.

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

Abstract: A measuring method includes the following. An image to be tested of an object to be tested with a first characteristic pattern is formed and is copied to form multiple images to be tested. The multiple images to be tested are superimposed to form a to-be-tested overlapped image which has the multiple first characteristic patterns. A reference image of a reference object with a second characteristic pattern is formed and is copied to form multiple reference images. The multiple reference images are superimposed to form a reference overlapped image which has the multiple second characteristic patterns. The to-be-tested overlapped image and the reference overlapped image are superimposed to generate a virtual moiré image having a moiré pattern different from the multiple first characteristic patterns and the multiple second characteristic patterns.

Abstract: A computer-implemented method includes receiving, by a computing system, an update for a computer program executing on the computing system. The method further includes determining, by the computing system, a data structure that is affected by the update by checking a structure change information included in the update. The method further includes checking, by the computing system, instance-count of the data structure, the instance-count representing a number of instances of the data structure in a memory of the computing system. The method further includes based on a determination that the instance-count is zero, applying, by the computing system, the update to the computer program.

Abstract: A task management method and device where the method includes determining, according to a foreground task, a first scenario corresponding to the foreground task, searching for at least one background task corresponding to the first scenario when the first scenario corresponding to the foreground task is in a first list, where the first list includes a scenario in which task limitation is allowed, and performing limitation processing on the at least one background task corresponding to the first scenario, where the limitation processing refers to processing for reducing system resource usage.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: A program control circuit for an antifuse-type one time programming memory cell array is provided. When the program action is performed, the program control circuit monitors the program current from the memory cell in real time and increases the program voltage at proper time. When the program control circuit judges that the program current generated by the memory cell is sufficient, the program control circuit confirms that the program action is completed.