Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first principal surface and a second principal surface. The silicon carbide substrate includes a drift region, a body region, and a source region. A gate trench is provided on the first principal surface. The silicon carbide substrate further includes a first reduced-electric field region provided between a bottom surface and the second principal surface. The source region includes a first region and a second region, and the first region is interposed between a side surface and the second region. The silicon carbide semiconductor device further includes a contact electrode with an ohmic junction with the second region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first principal surface; an interlayer insulating film; and a gate pad and a source pad provided on the film. The silicon carbide substrate includes a first region including unit cells; a second region overlapping the gate pad; and a third region. Each unit cell includes a drift region; a body region; a source region; a contact region; a gate electrode; and a gate insulating film. The second region includes a first semiconductor region. The third region includes a second semiconductor region. The first semiconductor region and the second semiconductor region are contiguous. In the interlayer insulation film, first and second contact holes are formed. The source pad is electrically connected to the source region and the contact region, electrically connected to the second semiconductor region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, and a gate pad and a source pad provided above a first main surface. The silicon carbide substrate includes a first region including unit cells, a second region overlapping the gate pad, and a third region continuous with the second region. Each of the unit cells includes a contact region electrically connected to a body region, and a gate insulating film provided between a gate electrode and a drift region, the body region, and a source region. The second region has a first semiconductor region of the second conductivity type. The third region has a second semiconductor region of the second conductivity type. The first semiconductor region and the second semiconductor region are continuous with each other along the first main surface. The source region, the contact region, and the second semiconductor region are electrically connected to the source pad.

Abstract: Silicon carbide semiconductor device includes silicon-carbide-substrate including first-main-surface and second-main-surface opposite to the first-main-surface; and insulating layer in contact with the first-main-surface. In plan-view from direction perpendicular to the first-main-surface, the silicon-carbide-substrate includes active region and termination region enclosing the active region. Opening where part of the active region is exposed is formed in the insulating layer. The silicon carbide semiconductor device further includes electrode formed on the insulating layer and in contact with the first-main-surface through the opening. The insulating layer includes first-portion overlapping the termination region and having first-thickness, in the plan-view; second-portion connecting to the first-portion, overlapping the electrode, and having second-thickness, in the plan-view; and third-portion connecting to the second-portion, overlapping the electrode, and having third-thickness, in the plan-view.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate that has first and second main surfaces and that includes a drift region being of a first-conductivity-type, a body region provided on the drift region and being of a second-conductivity-type, a source region provided on the body region and being of the first-conductivity-type, and a first electric field relaxation region being of the second-conductivity-type and including a first plane in which an impurity-concentration of the second-conductivity-type is a maximum and a second plane in which the impurity-concentration of the second-conductivity-type of 1/10 of the maximum, the second plane being closer to the second main surface than the first plane is. A distance between the first and second planes is 1.0 ?m or greater, and a distance from the first main surface to an interface between the first electric field relaxation region and the drift region is 2.0 ?m or greater.

Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having first and second main surfaces and including an electric field relaxation region and a connection region. A gate trench provided in the first main surface is defined by side surfaces and a bottom surface. The electric field relaxation region is a second conductivity type and provided between the bottom surface and the second main surface, and the connection region is the second conductivity type and electrically connects a contact region including first and second regions to the electric field relaxation region. In plan view, the gate trench and the electric field relaxation region are located on a virtual straight line. The first region is in contact with the connection region on the virtual straight line, and the second region is provided on a position where the source region is sandwiched between the gate trench and the second region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first principal surface and a second principal surface opposite to the first principal surface. The silicon carbide substrate includes a drift region, a body region, and a source region. A gate trench is provided on the first principal surface, the gate trench being defined by: a side surface, which passes through the source region and the body region and reaches the drift region; and a bottom surface coupled to the side surface. The silicon carbide substrate further includes a first reduced-electric field region provided between the bottom surface and the second principal surface and having a second conductive type. The source region includes a first region contacting the side surface, the first region having a first thickness. The source region includes a second region having a second thickness greater than the first thickness, the first region being interposed between the side surface and the second region.

Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.

Abstract: A semiconductor device includes a first layer of first conductivity type and including an element region where semiconductor elements are to be formed, an annular second layer of second conductivity type formed to include a surface of the first layer, and surrounding the element region in a plan view, a third layer of second conductivity type formed in the first layer and separated more from the surface than the second layer, and sandwiching a portion of the first layer between the second and third layers, a fourth layer of second conductivity type and electrically connecting the second and third layers, and an electrode electrically connected to the fourth layer inside the second layer in the plan view. effective concentration of a second conductivity type impurity included in the second layer is higher than that of the first layer, and lower than that of the third layer.

Abstract: A semiconductor device includes a first layer of first conductivity type and including an element region where semiconductor elements are to be formed, an annular second layer of second conductivity type formed to include a surface of the first layer, and surrounding the element region in a plan view, a third layer of second conductivity type formed in the first layer and separated more from the surface than the second layer, and sandwiching a portion of the first layer between the second and third layers, a fourth layer of second conductivity type and electrically connecting the second and third layers, and an electrode electrically connected to the fourth layer inside the second layer in the plan view. effective concentration of a second conductivity type impurity included in the second layer is higher than that of the first layer, and lower than that of the third layer.

Abstract: A magnetic resonance imaging apparatus according to the invention includes a magnet device that generates a static magnetic field and a gradient magnetic field in an imaging space, a top plate that is provided to freely travel on a bed and sends an object lying thereon into the imaging space, a top plate reception member that is disposed inside the imaging space and has a traveling surface of the top plate, a top plate support column that supports the top plate reception member, and a top plate support pedestal that supports a lower end of the top plate support column, in which the top plate support pedestal is provided on a floor surface on which the magnet device is provided, via a magnet support leg, and is provided so that a movement in a direction along at least the floor surface is restricted to the magnet support leg.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is famed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is famed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.