Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Abstract: A five-axis space precision measurement fixture includes a body, screw holes to install first balls and second balls. The body has a first surface, a second surface, a third surface and an inclined surface located with respect to the third surface between the first surface and the second surface. The first surface and the second surface are parallel to each other and are located on opposite sides of the third surface. An included angle between the inclined surface and the third surface is 45 degree. The first balls are equal-spacing into columns and rows on the first surface, and each of the first balls is protruded from the first surface along a first direction. The second balls are also equal-spacing disposed on the inclined surface, and each of the second balls is protruded from the inclined surface along a second direction which is vertical to the first direction.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: The present invention provides an image processing circuit and associated image processing method. In the image processing circuit, a characteristic value calculation circuit is designed to calculate the plurality of characteristic values of consecutive-three-pixels with increasing/decreasing brightness, the plurality of left-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness and the plurality of right-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness, for the brightness adjustments. The adjusted brightness values of the present invention have sharper edges to improve the image quality.

Abstract: A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.

Abstract: The present invention provides an image processing circuit including a receiving circuit, a reference value calculating circuit, a center luminance value calculating circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data. The reference value calculating circuit determines a first reference value and a second reference value corresponding to a plurality of pixels of the image data. The center luminance value calculating circuit refers to the first reference value and the second reference value to generate a center luminance value. The output circuit determines output luminance values of the plurality of pixel values according to the image data, the first reference value and the second reference value.

Abstract: A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.

Abstract: An image processing circuit capable of detecting an edge component includes: a selecting circuit acquiring the brightness values of pixels of an image according to the position of a target pixel and a processing region, wherein the pixels include N horizontal lines and M vertical lines; a brightness-variation calculating circuit generating N horizontal-line-brightness-variation values according to brightness variation of the N horizontal lines, and generating M vertical-line-brightness-variation values according to brightness variation of the M vertical lines; a brightness-variation determining circuit choosing a horizontal-line-brightness-variation representative value among the N horizontal-line-brightness-variation values, choosing a vertical-line-brightness-variation representative value among the M vertical-line-brightness-variation values, and choosing a brightness-variation representative value between the two representative values; an energy-variation calculating circuit generating an energy-variation

Abstract: A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Abstract: The present invention provides an image processing circuit and associated image processing method. In the image processing circuit, a characteristic value calculation circuit is designed to calculate the plurality of characteristic values of consecutive-three-pixels with increasing/decreasing brightness, the plurality of left-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness and the plurality of right-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness, for the brightness adjustments. The adjusted brightness values of the present invention have sharper edges to improve the image quality.

Abstract: The present invention discloses an image processing circuit, wherein the image processing circuit comprises a receiving circuit, a sharpness processing circuit, a luminance variation processing circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit is configured to receive image data; the sharpness processing circuit is configured to perform a high-pass filtering operation on the image data to generate processed image data; the luminance variation processing is configured to determine a high frequency component of each pixel within the image data, and for each pixel, the luminance variation processing circuit is configured to calculate a difference between high frequency components of the pixel and neighboring pixel(s) to generate auxiliary image data; and the output circuit is configured to generate output image according to the processed image data and the auxiliary image data.

Abstract: An ultrasonic cutter includes a tool holder and an ultrasonic oscillator. The tool holder has a lower circular air-out aisle defined by sleeving an inner ring and an outer ring. The inner ring has oppositely a first surface and a second surface, and the outer ring has oppositely a third surface and a fourth surface. A gap spacing the first surface from the third surface has an upper air inlet and a lower air outlet. The second surface has a lower inner inclined surface forming a first angle with the first surface. The fourth surface has an outer inclined surface forming a second angle with the third surface. The ultrasonic oscillator, disposed in a chamber of the tool holder spatially connected with the gap, is used for providing ultrasonic oscillation to a cutter. In addition, a cooling and chip diversion system for the ultrasonic cutter is also provided.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.