Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Abstract: A method and apparatus of prediction for video coding are disclosed. According to one method, a luma Intra prediction mode is determined for a corresponding luma block collocated with the current chroma block, where a predefined mode is assigned to the luma Intra prediction mode when the corresponding luma block collocated with the current chroma block satisfies one or more conditions. A chroma Intra prediction mode is determined for the current chroma block according to the luma Intra prediction mode. The current chroma block is then encoded or decoded according to the chroma Intra prediction mode. According to another method, a predefined mode is assigned to Intra prediction mode for the current block when the current block satisfies one or more conditions. The current block is then encoded or decoded according to the Intra prediction mode.

Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for a current block is determined, where the current template includes an inside current template including inside prediction samples or inside partially reconstructed samples inside the current block. The inside partially reconstructed samples are derived by adding a DC value of the current block to the inside prediction samples. Corresponding candidate reference templates associated with the current block are determined at a set of candidate locations. A location of a target reference template among the candidate reference templates that achieves a best match between the current template and the candidate reference templates is determined. An initial motion vector (MV) is then refined according to the location of the target reference template.

Abstract: A video coding system that uses template matching (TM) to improve signaling of coding modes is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies a set of pixels neighboring the current block as a current template. The system identifies a reference template of each candidate coding mode in a plurality of candidate coding modes. The system computes a template matching (TM) cost for each candidate coding mode based on matching the current template with the reference template of the candidate coding mode. The system selects a candidate coding mode from the plurality of candidate coding modes based on the computed TM costs. The system reconstructs the current block or encoding the current block into a bitstream by using selected candidate coding mode.

Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for the current block is determined, where at least one of current above template and current left template is removed or is located away from a respective above edge or a respective left edge of the current block and the current template is generated using reconstructed samples. Candidate reference templates, corresponding to the current template at respective candidate locations, associated with the current block at a set of candidate locations in a reference picture are determined. A location of a target reference template among the candidate reference templates is determined, where the target reference template achieves a best match with the current template. A refined motion vector (MV) is determined by refining an initial MV according to the location of the target reference template.

Abstract: A video coding system generating candidates for Merge Mode with Motion Vector Difference (MMVD) with reduced resource usage is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies multiple MMVD candidates for different offset positions based on a merge candidate of the current block. The system generates reference samples for the identified MMVD candidates. The system reconstructs the current block or encodes the current block into a bitstream by using the generated reference samples. The system processes the MMVD candidates in separate groups: a first group of vertical MMVD candidates and a second group of horizontal MMVD candidates. The system generates the reference samples for the identified MMVD candidates by applying a vertical filter to source reference samples of horizontal MMVD candidates and then applying a horizontal filter to outputs of the vertical filter.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: Provided is a recombinant microorganism including at least two genes for producing itaconic acid and its derived monomers, and the at least two genes are located on the same expression vector. The at least two genes include one encoding cis-aconitic acid decarboxylase and the other one encoding aconitase, and the genome of the recombinant microorganism includes a gene encoding the molecular chaperone protein GroELS. Also provided is a method for producing itaconic acid by using the microorganism.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.