Patents by Inventor Yu-Siang Yang

Yu-Siang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892026
    Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200379654
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
    Type: Application
    Filed: August 2, 2019
    Publication date: December 3, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Patent number: 10776053
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 15, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200227120
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 16, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200202935
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a read command for reading first data; obtaining a current first temperature of a rewritable non-volatile memory module according to the read command; obtaining a second temperature of the rewritable non-volatile memory module of writing the first data to a first physical programming unit according to the read command; and selecting a first decoding operation according to the first temperature and the second temperature and executing the first decoding operation.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 25, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Lih Yuarn Ou, Yu-Siang Yang
  • Patent number: 10685711
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a read command for reading first data; obtaining a current first temperature of a rewritable non-volatile memory module according to the read command; obtaining a second temperature of the rewritable non-volatile memory module of writing the first data to a first physical programming unit according to the read command; and selecting a first decoding operation according to the first temperature and the second temperature and executing the first decoding operation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 16, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Lih Yuarn Ou, Yu-Siang Yang
  • Publication number: 20200183623
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 11, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200168289
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 28, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10628259
    Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: April 21, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Siang Yang, Yu-Cheng Hsu
  • Publication number: 20200034232
    Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 30, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Siang Yang, Yu-Cheng Hsu
  • Publication number: 20190318791
    Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
    Type: Application
    Filed: June 8, 2018
    Publication date: October 17, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
  • Patent number: 10424391
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 24, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Patent number: 10324787
    Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 18, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Yu-Siang Yang, Kuo-Hsin Lai
  • Publication number: 20190114227
    Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 18, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Yu-Siang Yang, Kuo-Hsin Lai
  • Publication number: 20190088336
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 21, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Patent number: 10074433
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 11, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Cheng Hsu, Wei Lin, Yu-Siang Yang
  • Publication number: 20090023368
    Abstract: A polishing head used for CMP is described, including a retaining ring that is for engaging with a wafer, a membrane and an edge control ring. The membrane includes a bottom part for engaging with the wafer, and a lip part contiguous with the bottom part. The edge control ring is disposed between the retaining ring and the membrane, including a bottom part that has an abutting surface. The abutting surface of the edge control ring contacts with the external surface of the lip part of the membrane when the membrane is not inflated.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Hsin Wu, Tzu-Hung Yang, Shao-Wei Chen, Yi-Chin Liu, Yu-Siang Yang, Pei-Lin Kuo, Hui-Shen Shih