Patents by Inventor Yu-Tien Shen

Yu-Tien Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955338
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11901190
    Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Yuan Tseng, Yu-Tien Shen, Wei-Liang Lin, Chih-Ming Lai, Kuo-Cheng Ching, Shi Ning Ju, Li-Te Lin, Ru-Gun Liu
  • Patent number: 11901188
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Publication number: 20240047209
    Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Patent number: 11881401
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20240019787
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 18, 2024
    Inventors: Ru-Gun LIU, Huicheng Chang, Chia-Cheng Chen, Jyu-Horng Shieh, Liang-Yin Chen, Shu-Huei Suen, Wei-Liang Lin, Ya Hui Chang, Yi-Nien Su, Yung-Sung Yen, Chia-Fong Chang, Ya-Wen Yeh, Yu-Tien Shen
  • Patent number: 11862465
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Publication number: 20230411156
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 21, 2023
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Publication number: 20230386834
    Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Kai YANG, Yu-Tien SHEN, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Publication number: 20230369047
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.
    Type: Application
    Filed: July 30, 2023
    Publication date: November 16, 2023
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
  • Patent number: 11796922
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Jyu-Horng Shieh, Liang-Yin Chen, Shu-Huei Suen, Wei-Liang Lin, Ya Hui Chang, Yi-Nien Su, Yung-Sung Yen, Chia-Fong Chang, Ya-Wen Yeh, Yu-Tien Shen
  • Patent number: 11791161
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
  • Patent number: 11776810
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Publication number: 20230260803
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20230170218
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11651972
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Publication number: 20230061485
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Publication number: 20230049405
    Abstract: A method includes patterning a hard mask over a target layer, capturing a low resolution image of the hard mask, and enhancing the low resolution image of the hard mask with a first machine learning model to produce an enhanced image of the hard mask. The method further includes analyzing the enhanced image of the hard mask with a second machine learning model to determine whether the target layer has defects.
    Type: Application
    Filed: February 11, 2022
    Publication date: February 16, 2023
    Inventors: Chih-Kai Yang, Tung-Chin Wu, Yu-Tien Shen, Hsiang Ming Chang, Chun-Yen Chang, Ya Hui Chang, Zengqin Zhao
  • Patent number: 11569090
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20230023152
    Abstract: A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.
    Type: Application
    Filed: January 4, 2022
    Publication date: January 26, 2023
    Inventors: Hsin-Chih WANG, Yu-Tien SHEN, Yu-Tse LAI, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG