Patents by Inventor Yu-Tien Shen

Yu-Tien Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343097
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Publication number: 20200335340
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Publication number: 20200279743
    Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20200243336
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Application
    Filed: January 27, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Patent number: 10714357
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Patent number: 10707081
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Patent number: 10658184
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20200006085
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: April 12, 2019
    Publication date: January 2, 2020
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20190341254
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Shih-Chun HUANG, Chin-Hsiang LIN, Chien-Wen LAI, Ru-Gun LIU, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Yu-Tien SHEN, Ya-Wen YEH
  • Patent number: 10354874
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chin-Hsiang Lin, Chien-Wen Lai, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20190164772
    Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 30, 2019
    Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi Ning JU, Li-Te LIN, Ru-Gun LIU
  • Publication number: 20190157084
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Application
    Filed: August 21, 2018
    Publication date: May 23, 2019
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20190148145
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chun Huang, Chin-Hsiang Lin, Lai Chien Wen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20190148147
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 16, 2019
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Publication number: 20190067000
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
  • Publication number: 20180330960
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Patent number: 10032639
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Publication number: 20180174853
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Application
    Filed: March 30, 2017
    Publication date: June 21, 2018
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20170345670
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen