Patents by Inventor Yu-Ting Cheng

Yu-Ting Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7880305
    Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ting Cheng, Sherif A. Goma, John Harold Magerlein, Sampath Purushothaman, Carlos Juan Sambucetti, George Frederick Walker
  • Patent number: 7870378
    Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: January 11, 2011
    Assignee: Magic Pixel Inc.
    Inventors: Yu-Hao Kuo, Chi-Houn Ma, Yu-Ting Cheng, Chun-Chieh Huang, Hua-Lin Chang
  • Publication number: 20090302454
    Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.
    Type: Application
    Filed: August 11, 2009
    Publication date: December 10, 2009
    Inventors: Yu- Ting Cheng, Sherif A. Goma, John Harold Magerlein, Sampath Purushothaman, Carlos Juan Sambucetti, George Frederick Walker
  • Publication number: 20090227823
    Abstract: This invention relates to compositions and methods for fluid hydrocarbon product, and more specifically, to compositions and methods for fluid hydrocarbon product via catalytic pyrolysis. Some embodiments relate to methods for the production of specific aromatic products (e.g., benzene, toluene, naphthalene, xylene, etc.) via catalytic pyrolysis. Some such methods may involve the use of a composition comprising a mixture of a solid hydrocarbonaceous material and a heterogeneous pyrolytic catalyst component. In some embodiments, the mixture may be pyrolyzed at high temperatures (e.g., between 500° C. and 1000° C.). The pyrolysis may be conducted for an amount of time at least partially sufficient for production of discrete, identifiable biofuel compounds. Some embodiments involve heating the mixture of catalyst and hydrocarbonaceous material at high rates (e.g., from about 50° C. per second to about 1000° C. per second). The methods described herein may also involve the use of specialized catalysts.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: University of Massachusetts
    Inventors: George W. Huber, Yu-Ting Cheng, Torren Carlson, Tushar Vispute, Jungho Jae, Geoff Tompsett
  • Patent number: 7451415
    Abstract: In this invention, a closed-form integral model for on-chip suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and solid state physics to characterize a spiral inductor which RFIC designers could easily have the optimal design utilizing this analytical method. Meanwhile, this model can provide satisfactory prediction to the inductance and self-resonant frequency of the spiral inductor without complicated geometry analysis. Furthermore, unlike conventional formulations only based on circuit parameters, this model could safely predict the inductance and the self-resonant frequency when altering the material (excluding ferromagnetic materials) of a spiral inductor.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: November 11, 2008
    Assignee: National Chiao Tung University
    Inventors: Chien-Chang Chen, Yu-Ting Cheng
  • Publication number: 20080082814
    Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 3, 2008
    Applicant: Magic Pixel Inc.
    Inventors: Yu-Hao Kuo, Chi-Houn Ma, Yu-Ting Cheng, Chun-Chieh Huang, Hua-Lin Chang
  • Publication number: 20080008900
    Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Inventors: Yu-Ting Cheng, Stefanie Chiras, Donald Henderson, Sung-Kwon Kang, Stephen Kilpatrick, Henry Nye, Carlos Sambucetti, Da-Yuan Shih
  • Patent number: 7273803
    Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ting Cheng, Stefanie Ruth Chiras, Donald W. Henderson, Sung-Kwon Kang, Stephen James Kilpatrick, Henry A. Nye, III, Carlos J. Sambucetti, Da-Yuan Shih
  • Publication number: 20070214442
    Abstract: In this invention, a closed-form integral model for on-chip freely suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and solid state physics to characterize a spiral inductor which RFIC designers could easily have the optimal design utilizing this analytical method. Meanwhile, this model can provide satisfactory prediction to the inductance and self-resonant frequency of the spiral inductor without complicated geometry analysis. Furthermore, unlike conventional formulations only based on circuit parameters, this model could safely predict the inductance and the self-resonant frequency when altering the material (excluding ferromagnetic materials) of a spiral inductor.
    Type: Application
    Filed: May 18, 2006
    Publication date: September 13, 2007
    Inventors: Chien-Chang Chen, Yu-Ting Cheng
  • Publication number: 20060027934
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
  • Publication number: 20050118437
    Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 2, 2005
    Inventors: Yu-Ting Cheng, Stefanie Chiras, Donald Henderson, Sung-Kwon Kang, Stephen Kilpatrick, Henry Nye, Carlos Sambucetti, Da-Yuan Shih
  • Publication number: 20040089948
    Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dilectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.
    Type: Application
    Filed: November 7, 2002
    Publication date: May 13, 2004
    Inventors: Yu-Ting Cheng, Sherif A. Goma, John Harold Magerlein, Sampath Purushothaman, Carlos Juan Sambucetti, George Frederick Walker
  • Patent number: 6436853
    Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: August 20, 2002
    Assignee: University of Michigan
    Inventors: Liwei Lin, Yu-Ting Cheng, Khalil Najafi, Kensall D. Wise
  • Publication number: 20010021570
    Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.
    Type: Application
    Filed: February 27, 2001
    Publication date: September 13, 2001
    Inventors: Liwei Lin, Yu-Ting Cheng, Khalil Najafi, Kensall D. Wise
  • Patent number: 6232150
    Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: May 15, 2001
    Assignee: The Regents of the University of Michigan
    Inventors: Liwei Lin, Yu-Ting Cheng, Khalil Najafi, Kensall D. Wise