Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: A digital-to-time converter (DTC) includes a plurality of delay stages connected in series, in which each of the plurality of delay stages includes an input circuit and a delay circuit. The input circuit has a first input terminal, a second input terminal and a first output terminal, and is configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit. The delay circuit is coupled to the input circuit in series, and is configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal. The delay signal indicates a time interval corresponding to the digital control signal.

Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.

Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.

Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.

Abstract: A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.

Abstract: A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump. The second semiconductor layer has formed thereon a voltage controlled oscillator having an input and an output, and a feedback frequency divider circuit having an input coupled to the output of the voltage controlled oscillator and an input. A first interlayer via couples the loop filter circuit to the input of the voltage controlled oscillator circuit. A second interlayer via couples the output of the feedback frequency divider circuit to the feedback input of the phase frequency detector.

Abstract: A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.

Abstract: A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump. The second semiconductor layer has formed thereon a voltage controlled oscillator having an input and an output, and a feedback frequency divider circuit having an input coupled to the output of the voltage controlled oscillator and an input. A first interlayer via couples the loop filter circuit to the input of the voltage controlled oscillator circuit. A second interlayer via couples the output of the feedback frequency divider circuit to the feedback input of the phase frequency detector.

Abstract: A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.

Abstract: A signal processing system including a DAC, a comparing unit, and a control unit is provided. The DAC receives a digital input and generates an output voltage. The comparing unit receives the output voltage and compares the output voltage with a reference voltage to output an output value. The control unit receives the output value and accordingly generates the digital input in a manner of value mapping through firmware or software to calibrate the DAC. Furthermore, a self-calibration digital-to-analog converting method is also provided.

Abstract: This invention is primarily a circuit structure of self-mixing receiver, and the methodology of circuit structure is described as follows. The first stage is a high input impedance voltage amplifier utilized to amplify the received RF carrier signal from the antenna. Besides, there are no any inductors required. The second stage is a multi-stage amplifier to amplify the output signal of first stage to rail-to-rail level, which is quite the same with supply voltage. The third stage is a mixer adopted to lower the signal frequency. The fourth stage is a digital output converter, which is proposed to demodulate the electric signals and convert the demodulated signal to digital signal.

Abstract: A signal processing system including a DAC, a comparing unit, and a control unit is provided. The DAC receives a digital input and generates an output voltage. The comparing unit receives the output voltage and compares the output voltage with a reference voltage to output an output value. The control unit receives the output value and accordingly generates the digital input in a manner of value mapping through firmware or software to calibrate the DAC. Furthermore, a self-calibration digital-to-analog converting method is also provided.

Abstract: The present invention relates to an intra-body communication (IBC) device and a method of implementing the IBC device. The IBC device is fabricated as a system-on-a-chip (SOC) and comprises a first electrode, a second electrode, an IBC module and a biomedical chip. The first electrode is connected to a patient's skin. The second electrode is connected to the patient's skin. The IBC module is connected to the first electrode and comprises a wireless communication device. The biomedical chip is connected to the second electrode and communicates with the IBC module through the patient's skin to receive external commands and transmit sensed biomedical parameters to a faraway location.

Abstract: The present invention is a feed-forward automatic-gain control amplifier (FFAGCA) for biomedical applications and associated method, the FFAGCA comprises a detector, a controller, a variable gain amplifier (VGA), an input and an output. The associated method to process various kinds of biomedical signals with the FFAGCA comprises acts of adjusting gain setting with control path and simultaneously a signal amplification with signal path.

Abstract: The present invention relates to an intra-body communication (IBC) device and a method of implementing the IBC device. The IBC device is fabricated as a system-on-a-chip (SOC) and comprises a first electrode, a second electrode, an IBC module and a biomedical chip. The first electrode is connected to a patient's skin. The second electrode is connected to the patient's skin. The IBC module is connected to the first electrode and comprises a wireless communication device. The biomedical chip is connected to the second electrode and communicates with the IBC module through the patient's skin to receive external commands and transmit sensed biomedical parameters to a faraway location.