Patents by Inventor Yuan-Chen Sun

Yuan-Chen Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855141
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Publication number: 20220344330
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 11410996
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 11164864
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Publication number: 20210234003
    Abstract: A method of fabricating a device on a substrate includes doping a channel region of the device with dopants. The method further includes growing an undoped epitaxial layer over the channel region, wherein growing the undoped epitaxial layer comprises deactivating dopants in the channel region to form a deactivated region. The method further includes forming a gate structure over the deactivated region.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Ken-Ichi GOTO, Wei-Hao WU, Yuan-Chen SUN, Zhiqiang WU
  • Publication number: 20210226005
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Patent number: 11063128
    Abstract: A semiconductor device includes a fin having a first semiconductor material, the fin having a source/drain (S/D) region and a channel region, the S/D region providing a top surface and two sidewall surfaces; an isolation structure surrounding a bottom portion of the fin, wherein the S/D region of the fin above the isolation structure has a step profile in each of the two sidewall surfaces; a semiconductor film over the S/D region and having a doped second semiconductor material, the semiconductor film providing a top surface and two sidewall surfaces over the top and two sidewall surfaces of the fin respectively, wherein the doped second semiconductor material is different from the first semiconductor material; and a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 11043556
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Patent number: 10985246
    Abstract: A semiconductor device includes a channel region comprising dopants, a gate structure over the channel region and a deactivated region underneath the gate structure and partially within the channel region. Dopants within the deactivated region are deactivated. The deactivated region includes carbon. The deactivated region is physically separated from a top surface of a substrate by a portion of the substrate that is free of carbon.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun
  • Publication number: 20200006337
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Publication number: 20190393305
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Application
    Filed: May 7, 2019
    Publication date: December 26, 2019
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Publication number: 20190165104
    Abstract: A semiconductor device includes a channel region comprising dopants, a gate structure over the channel region and a deactivated region underneath the gate structure and partially within the channel region. Dopants within the deactivated region are deactivated. The deactivated region includes carbon. The deactivated region is physically separated from a top surface of a substrate by a portion of the substrate that is free of carbon.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Wei-Hao WU, Ken-Ichi GOTO, Zhiqiang WU, Yuan-Chen SUN
  • Publication number: 20190123157
    Abstract: A semiconductor device includes a fin having a first semiconductor material, the fin having a source/drain (S/D) region and a channel region, the S/D region providing a top surface and two sidewall surfaces; an isolation structure surrounding a bottom portion of the fin, wherein the S/D region of the fin above the isolation structure has a step profile in each of the two sidewall surfaces; a semiconductor film over the S/D region and having a doped second semiconductor material, the semiconductor film providing a top surface and two sidewall surfaces over the top and two sidewall surfaces of the fin respectively, wherein the doped second semiconductor material is different from the first semiconductor material; and a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 10269791
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 10164033
    Abstract: A semiconductor device includes a fin having a first semiconductor material. The fin includes a source/drain (S/D) region and a channel region. The S/D region provides a top surface and two sidewall surfaces. A width of the S/D region is smaller than a width of the channel region. The semiconductor device further includes a semiconductor film over the S/D region and having a doped second semiconductor material that is different from the first semiconductor material. The semiconductor film provides a top surface and two sidewall surfaces over the top and two sidewall surfaces of the S/D region respectively. The semiconductor device further includes a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 10157985
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun
  • Publication number: 20180350806
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 6, 2018
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Publication number: 20170194442
    Abstract: A semiconductor device includes a fin having a first semiconductor material. The fin includes a source/drain (S/D) region and a channel region. The S/D region provides a top surface and two sidewall surfaces. A width of the S/D region is smaller than a width of the channel region. The semiconductor device further includes a semiconductor film over the S/D region and having a doped second semiconductor material that is different from the first semiconductor material. The semiconductor film provides a top surface and two sidewall surfaces over the top and two sidewall surfaces of the S/D region respectively. The semiconductor device further includes a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Application
    Filed: March 2, 2017
    Publication date: July 6, 2017
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 9614086
    Abstract: A semiconductor device includes a fin having a first semiconductor material. The fin includes a source/drain (S/D) region and a channel region. The S/D region provides a top surface and two sidewall surfaces. A width of the S/D region is smaller than a width of the channel region. The semiconductor device further includes a semiconductor film over the S/D region and having a doped second semiconductor material. The semiconductor film provides a top surface and two sidewall surfaces that are substantially parallel to the top and two sidewall surfaces of the S/D region respectively. The semiconductor device further includes a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun
  • Publication number: 20160276343
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Application
    Filed: January 20, 2016
    Publication date: September 22, 2016
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun