Patents by Inventor Yuan-Shun Chang

Yuan-Shun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120299109
    Abstract: A fabrication method of trench power semiconductor structure with high switching speed is provided. An epitaxial layer with a first conductivity type is formed on a substrate. Then, gate structures are formed in the epitaxial layer. A shallow doped region with the first conductivity type is formed in the surface layer of the epitaxial layer. After that, a shielding structure is formed on the shallow doped region. Then, wells with a second conductivity type are formed in the epitaxial layer by using the shielding structure as an implantation mask. Finally, a source doped region with the first conductivity type is formed on the surface of the well. The doping concentration of the shallow doped layer is smaller than that of the source doped region and the well. The doping concentration of the shallow doped layer is larger than that of the epitaxial layer.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: GREAT POWER SEMICONDUCTOR CORP.
    Inventors: YUAN-SHUN CHANG, KAO-WAY TU
  • Publication number: 20120299091
    Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: GREAT POWER SEMICONDUCTOR CORP.
    Inventors: YI-YUN TSAI, YUAN-SHUN CHANG, KAO-WAY TU
  • Publication number: 20110318895
    Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
    Type: Application
    Filed: September 6, 2011
    Publication date: December 29, 2011
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventors: Kou-Way Tu, Hsiu-Wen Hsu, Yi-Yun Tsai, Yuan-Shun Chang