Abstract: A method and associated arrangement for use in priority allocation in a bus interconnected digital multi-module system are disclosed. The modules are configured for requesting the use of the bus with each module being granted its request based upon its priority. During the operation of the system, a set of priorities is established such that the number of priorities is equal to the number of modules in the system. Each module is assigned to an initial priority. During the operation of the system, modules may be reassigned to a priorities which are different than their initial priorities. In addition, the priorities may be grouped in an initial group arrangement which may be reconfigured. The group arrangement may be reconfigured in any desired manner. Also, provisions are made for refusing a grant to a module even though that module possesses the highest priority among requesting modules.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements.

Abstract: Electrical contact terminals having two layer plated coating thereon is disclosed. The coating consists of a layer of palladium having a macrostress in the range of 30,000 to 140,000 psi and a layer of gold, the gold being at lest 99.9% pure and having a Knoop hardness from 60 to 90. A coating comprised of medium stress palladium and gold substantially and unexpectedly inmproves the durability of terminals as compared to similar coatings using gold and low or high stress palladium.

Abstract: A method and uroflowmeter apparatus for measuring uroflow parameters by flow impulse momentum, providing measurement and print out in real time of such parameters as the flow rate curve and of maximum flow rate, average flow rate, voided volume, voiding time, flow time, and time to maximum flow rate, necessary for medical diagnosis.

Abstract: Disclosed is an electrical connector transferring device, comprising: a first plastic member having at least one row of first upper through holes and at least one row of first lower through holes; a second plastic member having at least one row of second upper through holes corresponding with said one row of first lower through holes, and at least one row of second lower through holes corresponding with said one row of first upper through holes; a first intermediate block having a set of first grooves corresponding with to said one row of first upper through holes, and a set of second grooves corresponding with said one row of first lower through holes, said first intermediate block being assembled to said first plastic member; a second intermediate block having a set of third grooves corresponding with said one row of second lower through holes, and a set of fourth grooves corresponding with said one row of second upper through holes, said second intermediate block being assembled between said first intermed