Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: A file access method, a system, and a host are provided. According to the method, after obtaining information about first virtual space of a target file, a host allocates, in local virtual address space of the host, second virtual space to the target file, where the first virtual space is space allocated in global virtual address space by a management node in a distributed storage system to the target file. The host converts, according to a correspondence between the first virtual space and the second virtual space, a second access request of accessing the second virtual space into a first access request, where an address of the first virtual space in the first access request includes device information of a first storage node. Then, the host sends the first access request to a network device to route the first access request to the first storage node.

Abstract: A write request processing method and a memory controller, where the method includes, determining a second write request set, by the memory controller, after determining that a quantity of write requests in a to-be-scheduled first write request set is less than a quantity of unoccupied storage units in a memory, where the write request in the first write request set is located before a first memory barrier, where a write request in the second write request set is a log write request, and where the write request in the second write request set is located behind the first memory barrier. The memory controller sends the write request in the first write request set and the write request in the second write request set in parallel to different unoccupied storage units in the memory.

Abstract: A memory extensible chip (200) is provided. The chip (200) includes a substrate (240), and a processor (230), a first memory module set (210), and a second memory module set (220) that are integrated on the substrate (240). The processor (230) communicates with at least one memory module in the first memory module set (210) using a first communications interface (250), and the processor (230) communicates with at least one memory module in the second memory module set (220) using a second communications interface (260). A memory module in the first memory module set (210) communicates with a memory module in the second memory module set (220) using a substrate network, where the substrate network is a communications network located inside the substrate (240). In this way, the processor (230) can access a memory module in the first memory module set (210) by using the second memory module set (220).

Abstract: A data access method, a routing apparatus, and a storage system are provided. The method is applied to a storage system including a first storage device, a second storage device, and a routing apparatus. A logical unit in each storage device includes at least one first-type logical block and at least one second-type logical block. According to the method, when sending access requests to the storage devices in the storage system according to a preset rule, the routing apparatus sends access requests corresponding to same target logical blocks to one of the storage devices according to a preset rule. This reduces network overheads between the storage system and the application server, and improves efficiency of processing the access requests by the storage system.

Abstract: A data migration method for a storage system after expansion and a storage system are provided. After an ith expansion is performed on the storage system, data migration is performed by using an auxiliary balanced incomplete block design. Because a quantity of tuples including any element in the auxiliary balanced incomplete block design is identical, and each migration unit includes an identical quantity of parity chunks, a data migration amount after the expansion is minimized. In this way, time required for data migration after the expansion is significantly reduced, and a delay in a response to a user request that is caused because a data migration operation needs to be performed after the expansion is also reduced.

Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.

Abstract: A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.

Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.

Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.

Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends update data chunk obtained from to-be-written data to corresponding storage node. The storage node do not directly update, based on the received update data chunks, data block stored in storage device of the storage node, but store the update data chunk into non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node to backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.

Abstract: A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

Abstract: An access request processing method and apparatus, and a computer device are disclosed. The computer device includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.

Abstract: A file access method and apparatus, and a storage device are presented, where the file access method is applied to a storage device in which a file system is established based on a memory. The storage device obtains, according to a file identifier of a to-be-accessed first target file, an index node of the first target file in metadata, where the index node of the first target file stores information about first virtual space of the first target file in global virtual space. The storage device maps the first virtual space onto second virtual space of a process, and performs addressing on an added file management register to access the first target file according to a start address of the first virtual space and a base address of a page directory of the global file page table stored in the file management register.

Abstract: A file data access method and a computer system, where the method includes accessing a page global directory (PGD) of the process using PGD space when accessing first file data by a process, determining, based on access to the PGD and according to a first virtual address of the first file data in file system space, a first PGD entry in the PGD, linking a file page table of the process to the first PGD entry, where the file page table points to a physical address of the file data such that a processor retrieves a first physical address of the first file data in a memory according to the first virtual address using the PGD and the file page table, and accessing the first file data according to the first physical address.

Abstract: A write request processing method and a memory controller, where the method includes, determining a second write request set, by the memory controller, after determining that a quantity of write requests in a to-be-scheduled first write request set is less than a quantity of unoccupied storage units in a memory, where the write request in the first write request set is located before a first memory barrier, where a write request in the second write request set is a log write request, and where the write request in the second write request set is located behind the first memory barrier. The memory controller sends the write request in the first write request set and the write request in the second write request set in parallel to different unoccupied storage units in the memory.

Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.