Patents by Inventor Yuanlong Wang

Yuanlong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10558608
    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 11, 2020
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Publication number: 20200026676
    Abstract: The present invention discloses a USB expansion function device. When the USB expansion function device with batteries is connected to a mobile terminal device that needs to be charged, by limiting a charging current through a current limiter, a data communication function of the USB expansion function device connected to the mobile terminal device in a USB host mode is implemented while low power consumption of the batteries inside the USB expansion function device is ensured. Thus, the USB expansion function device with batteries can operate continuously for a long time, and its compatibility with data connection of the mobile terminal device can be improved.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 23, 2020
    Inventors: Wei ZHAO, Rui ZHU, Ting WU, Lulu XU, Yuanlong WANG
  • Publication number: 20190392875
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: July 1, 2019
    Publication date: December 26, 2019
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20190250973
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 15, 2019
    Inventors: Yuanlong WANG, Frederick A. WARE
  • Patent number: 10366143
    Abstract: A method and system for selecting an encoding format used for reading a target document are provided. The method comprises reading a reference document with at least one reference encoding format and determining all or some disorder code patterns obtained when reading the reference document with the reference encoding format; reading the target document with one encoding format each time; for each encoding format, comparing data generated when reading the target document with this encoding format and the determined disorder code patterns to determine disorder codes generated when reading the target document with this encoding format; counting disorder codes generated when reading the target document with each encoding format, and making a comparison to determine the encoding format used for reading the target document.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: July 30, 2019
    Assignee: PEKING UNIVERSITY FOUNDER GROUP CO., LTD.
    Inventors: Mao Ye, Wei Wan, Lifeng Jin, Yuanlong Wang
  • Patent number: 10339990
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 2, 2019
    Assignee: RAMBUS INC.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 10289623
    Abstract: A method and system for key knowledge point recommendation are provided, the method comprising calculating knowledge point relationship strengths of knowledge points in a set of knowledge points; calculating weights for knowledge points according to the knowledge point relationship strengths of knowledge points in the set of knowledge points, and storing the knowledge points and weights correspondingly; determining key knowledge points according to the weights of the knowledge points and recommending the key knowledge points to a user.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 14, 2019
    Assignees: PEKING UNIVERSITY FOUNDER GROUP CO. LTD., FOUNDER APABI TECHNOLOGY LIMITED, PEKING UNIVERSITY
    Inventors: Mao Ye, Jianbo Xu, Zhi Tang, Lifeng Jin, Yuanlong Wang
  • Patent number: 10241849
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 26, 2019
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20190052105
    Abstract: A method for automatically identifying Apple and Android devices is provided, allowing a mobile charging apparatus to charge a charged device and perform USB data communication. The mobile charging apparatus enumerates the charged device in a USB Host mode to obtain VID information. If the VID information indicates that the charged device is an Apple device, the mobile charging apparatus switches to a USB Device mode, the charged device switches to the USB Host mode, and the charged device performs subsequent USB data communication with the mobile charging apparatus. If the VID information indicates that the charged device is an Android device, the mobile charging apparatus maintains the USB Host mode, the charged device maintains the USB Device mode, and the mobile charging apparatus performs subsequent USB data communication with the charged device. While performing USB data communication, the mobile charging apparatus can also charge the charged device.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 14, 2019
    Inventors: Hui WANG, Ting Wu, Wei Zhao, Yuanlong Wang
  • Publication number: 20190050037
    Abstract: An intelligent mobile power supply and a method for USB data communication therewith. The intelligent mobile power supply includes a battery, a charging control module, a discharging control module, a first USB interface and a second USB interface. In the single charging mode, a charged device receives a discharge of the intelligent mobile power supply through the discharging control module, but the intelligent mobile power supply does not perform USB data communication with the charged device. While in the charging and communication mode, the charged device receives the discharge of the intelligent mobile power supply through the discharging control module and can perform USB data communication with the intelligent mobile power supply through the first USB interface simultaneously. The second USB interface is connected with the charging control module, and the second USB interface can be connected with a power adapter or a PC host to charge the battery.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 14, 2019
    Inventors: Yuanlong WANG, Ting Wu, Wei Zhao, Miao Chen
  • Patent number: 10180865
    Abstract: A memory device includes a first interface that is to couple to a bidirectional link and a second interface to couple to a unidirectional link. An encoder generates first error-detection information corresponding to write data received via the bidirectional link for a write operation. An encoder generates second error-detection information corresponding to read data transmitted via the bidirectional link for a read operation. A transmitter coupled to the unidirectional link transmits the both the first and second error-detection information. A controller may receive the first and second error-detection information. Based on at least one of the first and second error-detection information, the controller may command the memory device to retry an operation.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 15, 2019
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20180322002
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Yuanlong WANG, Frederick A. WARE
  • Publication number: 20180210779
    Abstract: A memory device includes a first interface that is to couple to a bidirectional link and a second interface to couple to a unidirectional link. An encoder generates first error-detection information corresponding to write data received via the bidirectional link for a write operation. An encoder generates second error-detection information corresponding to read data transmitted via the bidirectional link for a read operation. A transmitter coupled to the unidirectional link transmits the both the first and second error-detection information. A controller may receive the first and second error-detection information. Based on at least one of the first and second error-detection information, the controller may command the memory device to retry an operation.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 26, 2018
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20180107623
    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Application
    Filed: October 26, 2017
    Publication date: April 19, 2018
    Inventor: Yuanlong Wang
  • Publication number: 20180082725
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: July 31, 2017
    Publication date: March 22, 2018
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 9875151
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 23, 2018
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20170366016
    Abstract: A charging detection and control apparatus for an Apple device, including: a charging input interface, a detection apparatus, a control apparatus and a charging output interface. An input terminal of the detection apparatus is connected to a charging source terminal via the charging input interface, an output terminal of the detection apparatus is connected to an input terminal of the control apparatus, an output terminal of the control apparatus is connected to the Apple device via the charging output interface, the detection apparatus detects a capacity for charging current of the charging source terminal inserted into the charging input interface, and outputs a detection result to the control apparatus, the control apparatus converts the received detection result into a charging parameter complying with Apple standards, and sends the charging parameter to the Apple device via the charging output interface.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Inventors: Wei Zhao, Yuanlong Wang, Ting Wu, Hui Wang
  • Patent number: 9824056
    Abstract: The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: November 21, 2017
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Patent number: 9721630
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: August 1, 2017
    Assignee: RAMBUS INC.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20170147421
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 25, 2017
    Inventors: Yuanlong Wang, Frederick A. Ware