Patents by Inventor Yuanlong Wang

Yuanlong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140140149
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: August 5, 2013
    Publication date: May 22, 2014
    Applicant: Rambus Inc.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 8656254
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 18, 2014
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 8504788
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 6, 2013
    Assignee: Rambus Inc.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20130139019
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: January 28, 2013
    Publication date: May 30, 2013
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 8365042
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: January 29, 2013
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20120240010
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: February 16, 2012
    Publication date: September 20, 2012
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20120210157
    Abstract: The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Application
    Filed: October 29, 2010
    Publication date: August 16, 2012
    Applicant: RAMBUS INC.
    Inventor: Yuanlong Wang
  • Patent number: 7882423
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 1, 2011
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 7836378
    Abstract: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 16, 2010
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig Hampel, Yuanlong Wang, Fred Ware
  • Patent number: 7831888
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: November 9, 2010
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20100039875
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: December 19, 2007
    Publication date: February 18, 2010
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 7656321
    Abstract: In a signaling system, a first signal and a plurality of second signals are received via a signaling channel. A first received data value is generated in one of at least two states according to whether the first signal exceeds an average of the second signals.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: February 2, 2010
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Publication number: 20090249156
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 1, 2009
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20090249139
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 1, 2009
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Publication number: 20080163007
    Abstract: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction.
    Type: Application
    Filed: February 21, 2008
    Publication date: July 3, 2008
    Applicant: Rambus Inc.
    Inventors: Ian Shaeffer, Craig Hampel, Yuanlong Wang, Fred Ware
  • Publication number: 20070162825
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 12, 2007
    Inventors: Yuanlong Wang, Frederick Ware
  • Publication number: 20070009018
    Abstract: In a signaling system, a first signal and a plurality of second signals are received via a signaling channel. A first received data value is generated in one of at least two states according to whether the first signal exceeds an average of the second signals.
    Type: Application
    Filed: June 2, 2005
    Publication date: January 11, 2007
    Inventor: Yuanlong Wang
  • Patent number: 7142555
    Abstract: Data cells arriving in a switching unit are routed to virtual output queues. Load balancing method selects switching elements based on a dynamic utilization tracked by request virtual output queues that store switching requests from the virtual output queues.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: November 28, 2006
    Assignee: Mindspeed Technologies, Inc.
    Inventor: Yuanlong Wang
  • Patent number: 7028134
    Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: April 11, 2006
    Assignee: Conexant Systems, Inc.
    Inventors: Yuanlong Wang, Kewei Yang, Daniel Fu, Feng Cheng Lin
  • Publication number: 20040083326
    Abstract: A method and apparatus is disclosed for scheduling connections in a switch, such as an input-queued crossbar switch. In such an embodiment each input queue generates and provide requests for access to an egress port to a grant arbiter group. Each arbiter of the grant arbiter group grants a request from the two or more received request based on round robin scheduling of all available requests. Each of the grant arbiters notifies a accept arbiter group of the grants. Each arbiter in the accept arbiter group may receive more than one grant. Each arbiter in the accept arbiter group accepts a grant from the one or more grants received from the first arbiters based on least recently accepted scheduling. The accepted grants of the arbiters of the second arbiter groups control switch connections. In one embodiment the round robin scheduling and least recently accepted scheduling are updated after every iteration.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 29, 2004
    Inventors: Yuanlong Wang, Libin Dong