Abstract: This disclosure provides an array substrate, including: a display region and a peripheral region. The peripheral region includes at least one first sensor. The first sensor includes a photodiode and a driving circuit which are electrically connected to each other. The photodiode includes: an anode, a cathode and a photosensitive material layer. The array substrate includes: a base substrate, a plurality of thin film transistors, a common electrode and a pixel electrode. The common electrode is reused as an anode of the photodiode. The pixel electrode is reused as a cathode of the photodiode. One of the plurality of thin film transistors is reused as a first transistor of the driving circuit.

Abstract: The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: Provided are a display substrate and a display device. In the display substrate, the first separation structure includes a first separation part and a second separation part which are stacked, the second separation structure includes a third separation part and a fourth separation part which are stacked, the second separation part has a first protruding part, the first protruding part protrudes relative to the first separation part, and at least one sub-functional layer of the light-emitting functional layer is disconnected at the first protruding part; the fourth separation part has a second protruding part, the second protruding part protrudes relative to the third separation part, and at least one sub-functional layer of the light-emitting functional layer is disconnected at the second protruding part; the first separation structure surrounds the light-emitting region; and the second separation structure is ring-shaped so as to surround the hole region.

Abstract: A method may include obtaining various cross-spread gathers regarding a geological region of interest. The method may further include determining traveltime table data based on the cross-spread gathers. The method may further include transmitting the cross-spread gathers to various parallel processing groups in a parallel processing network. A respective cross-spread gather among the cross-spread gathers may be transmitted to a respective parallel processing group among the parallel processing groups. The method may further include determining, by various parallel processing nodes in the respective parallel processing group, a first subset of a migrated dataset using the respective cross-spread gather, a subset of the traveltime table data, a velocity model, and a migration function. The method may further include generating, based on various subsets of the migrated dataset that includes the first subset, a first seismic image of the geological region of interest.

Abstract: A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Abstract: This disclosure provides an array substrate, including: a display region and a peripheral region. The peripheral region includes at least one first sensor. The first sensor includes a photodiode and a driving circuit which are electrically connected to each other. The photodiode includes: an anode, a cathode and a photosensitive material layer. The array substrate includes: a base substrate, a plurality of thin film transistors, a common electrode and a pixel electrode. The common electrode is reused as an anode of the photodiode. The pixel electrode is reused as a cathode of the photodiode. One of the plurality of thin film transistors is reused as a first transistor of the driving circuit.

Abstract: An antenna structure and an electronic device, where the antenna structure includes: a reference floor; and a radiator, where the radiator and the reference floor are stacked and spaced apart, and the radiator includes a feeding point and a first current distribution part and a second current distribution part that are respectively located at two ends of the radiator; where a cross-polarization current direction on the first current distribution part is opposite to a cross-polarization current direction on the second current distribution part under the effect of a feeding signal input on the feeding point.

Abstract: A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Abstract: A technology for flushing a translation lookaside buffer (TLB) according to a designated key identification code (designated key ID). An instruction of an instruction set architecture is proposed to flush the TLB according to the designated key ID. A decoder transforms the instruction into at least one microinstruction. According to a flushing microinstruction included in the at least one microinstruction, a designated key ID is supplied to a control logic circuit of the TLB through a memory order buffer, so that the control logic circuit flushes matched entries in the TLB, wherein the matched entries match the designated key ID.

Abstract: A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Abstract: A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Abstract: Disclosed is a catalyst for preparing 2,3,3,3-tetrafluoropropene by gas-phase hydrodechlorination, which solves the problem of the high costs and easy deactivation of traditional chlorofluorocarbon hydrodechlorination catalysts. The disclosed catalyst is characterized in consisting of an active component and a carrier, wherein the active component is a combination of one or more of the metals: Ni, Mo, W, Co, Cr, Cu, Ce, La, Mn and Fe. The catalyst in the present invention has excellent performance, high activity, good stability and a low reaction temperature, effectively reduces reaction energy consumption, and has industrial application value.

Abstract: Disclosed is a catalyst for preparing 2,3,3,3-tetrafluoropropene by gas-phase hydrodechlorination, which solves the problem of the high costs and easy deactivation of traditional chlorofluorocarbon hydrodechlorination catalysts. The disclosed catalyst is characterized in consisting of an active component and a carrier, wherein the active component is a combination of one or more of the metals: Ni, Mo, W, Co, Cr, Cu, Ce, La, Mn and Fe. The catalyst in the present invention has excellent performance, high activity, good stability and a low reaction temperature, effectively reduces reaction energy consumption, and has industrial application value.

Abstract: The present application relates to a detection method, belonging to the technical field of anti-fake detection. The detection method comprises steps of: acquiring reference imaging spectral data and imaging spectral data of a surface of an object to be detected; obtaining spectral reflectance of the surface of the object to be detected according to the reference imaging spectral data and the imaging spectral data of the surface of the object to be detected; matching the spectral reflectance of the object to be detected with spectral reflectance, stored in a calibration library, of an original object corresponding to the object to be detected; determining that the object to be detected is consistent with the original object if the matching of spectral reflectance is successful; and determining that the object to be detected is not consistent with the original object if the matching of spectral reflectance is failed.

Abstract: The present disclosure provides an electronic apparatus and a method for producing a housing, which relate to a technical field of electronics. The electronic apparatus comprises: a housing comprising a side wall forming an accommodating space and having an outer surface which is divided into K appearance layers, where K is a positive integer greater than or equal to 3, and wherein borderlines between adjacent layers in the K appearance layers are parallel to each other.

Abstract: The present application relates to a detection method, belonging to the technical field of anti-fake detection. The detection method comprises steps of: acquiring reference imaging spectral data and imaging spectral data of a surface of an object to be detected; obtaining spectral reflectance of the surface of the object to be detected according to the reference imaging spectral data and the imaging spectral data of the surface of the object to be detected; matching the spectral reflectance of the object to be detected with spectral reflectance, stored in a calibration library, of an original object corresponding to the object to be detected; determining that the object to be detected is consistent with the original object if the matching of spectral reflectance is successful; and determining that the object to be detected is not consistent with the original object if the matching of spectral reflectance is failed.