Patents by Inventor Yueh-Chuan Lee

Yueh-Chuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040258932
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Application
    Filed: July 19, 2004
    Publication date: December 23, 2004
    Applicant: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Patent number: 6821842
    Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: November 23, 2004
    Assignee: ProMOS Technologies Inc.
    Inventors: Yueh-Chuan Lee, Shih-Lung Chen
  • Publication number: 20040229426
    Abstract: A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching process is conducted to etch the substrate down to the doped region to form a shallow trench. Thereafter, an isolating material is filled into the shallow trench to form an STI layer. The doped region is located directly under the STI layer, and no doped region is formed in the sidewall of the shallow trench.
    Type: Application
    Filed: September 29, 2003
    Publication date: November 18, 2004
    Inventors: Yueh-Chuan Lee, Jason Chen
  • Publication number: 20040198005
    Abstract: A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
    Type: Application
    Filed: October 30, 2003
    Publication date: October 7, 2004
    Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
  • Patent number: 6774461
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: August 10, 2004
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Publication number: 20040121166
    Abstract: A method of manufacturing a semiconductor device comprises the steps as follow. After forming an insulating layer with opening therein over a substrate, a polysilicon layer that partially fills the opening is formed over the substrate and then a refractory metal silicide layer that completely fills the opening is formed over the substrate. Thereafter, the polysilicon layer and the refractory metal silicide layer outside the opening are removed to expose the insulating layer. A portion of the polysilicon layer and the refractory metal silicide layer are etched back so that the surface of the polysilicon layer and the refractory metal silicide layer are below the surface of the insulating layer. After forming a cap layer over the polysilicon layer and the refractory metal silicide layer, the insulating layer is removed and then a liner layer is formed on the sidewalls of the polysilicon layer.
    Type: Application
    Filed: April 3, 2003
    Publication date: June 24, 2004
    Inventors: Bai-rou Ni, Fang-Yu Yeh, Yueh-Chuan Lee
  • Publication number: 20040079979
    Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.
    Type: Application
    Filed: December 24, 2002
    Publication date: April 29, 2004
    Inventors: Yueh-Chuan Lee, Shih-Lung Chen
  • Publication number: 20040051183
    Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
    Type: Application
    Filed: December 27, 2002
    Publication date: March 18, 2004
    Applicant: Promos Technologies, Inc.
    Inventors: Ming-Sheng Tung, Yueh-Chuan Lee
  • Patent number: 6680237
    Abstract: A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: January 20, 2004
    Assignee: ProMos Technologies Inc.
    Inventors: Shih-Lung Chen, Hsiao-Lei Wang, Hwei-Lin Chuang, Yueh-Chuan Lee
  • Publication number: 20030199135
    Abstract: A method of forming capacitor dielectric structure, comprising steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process to form a nitridation layer on the oxide layer.
    Type: Application
    Filed: May 15, 2003
    Publication date: October 23, 2003
    Applicant: ProMOS Technologies Inc.
    Inventors: Yueh-Chuan Lee, Shih-Lung Chen, Jin-Shing Huang, Wen-Sheng Lee
  • Publication number: 20030119238
    Abstract: A method of forming capacitor dielectric structure, comprising steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process to form a nitridation layer on the oxide layer.
    Type: Application
    Filed: December 26, 2001
    Publication date: June 26, 2003
    Inventors: Yueh-Chuan Lee, Shih-Lung Chen, Jin-Shing Huang, Wen-Sheng Lee
  • Publication number: 20030017675
    Abstract: A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.
    Type: Application
    Filed: September 27, 2001
    Publication date: January 23, 2003
    Inventors: Shih-Lung Chen, Hsiao-Lei Wang, Hwei-Lin Chuang, Yueh-Chuan Lee
  • Publication number: 20020182851
    Abstract: The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.
    Type: Application
    Filed: March 28, 2002
    Publication date: December 5, 2002
    Applicant: NATIONAL SCIENCE COUNCIL
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chien-Hsing Lin
  • Patent number: 6486057
    Abstract: The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 26, 2002
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chien-Hsing Lin
  • Publication number: 20020142580
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Application
    Filed: February 15, 2002
    Publication date: October 3, 2002
    Applicant: NATIONAL SCIENCE COUNCIL
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Patent number: 6294832
    Abstract: The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 25, 2001
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Kwo-Hau Wu, Yuh-Ching Su
  • Patent number: 6251753
    Abstract: A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: June 26, 2001
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Yuh-Ching Su, Kwo-Hau Wu