Patents by Inventor Yueh-Se Ho

Yueh-Se Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150340301
    Abstract: A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
  • Patent number: 9196534
    Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.
    Type: Grant
    Filed: February 24, 2013
    Date of Patent: November 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yan Xun Xue, Ping Huang, Hamza Yilmaz, Yueh-Se Ho, Lei Shi, Liang Zhao, Ping Li Wu, Lei Duan, Yuping Gong
  • Publication number: 20150325559
    Abstract: The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu
  • Patent number: 9184117
    Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: November 10, 2015
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yueh-Se Ho, Yan Xun Xue, Hamza Yilmaz, Jun Lu
  • Patent number: 9171788
    Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 27, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
  • Patent number: 9165866
    Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: October 20, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaotian Zhang, Yan Xun Xue, Anup Bhalla, Jun Lu, Kai Liu, Yueh-Se Ho, John Amato
  • Publication number: 20150262925
    Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
  • Patent number: 9136154
    Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: September 15, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
  • Patent number: 9136379
    Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 15, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yueh-Se Ho, Yan Xun Xue, Ping Huang
  • Publication number: 20150249045
    Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu
  • Publication number: 20150243589
    Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Inventors: Yueh-Se Ho, Hamza Yilmaz, Yan Xun Xue, Jun Lu
  • Publication number: 20150228729
    Abstract: A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.
    Type: Application
    Filed: February 26, 2015
    Publication date: August 13, 2015
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 9040356
    Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 26, 2015
    Assignee: Vishay-Siliconix
    Inventors: Mike Chang, King Owyang, Yueh-Se Ho, Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
  • Publication number: 20150102425
    Abstract: A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.
    Type: Application
    Filed: October 12, 2013
    Publication date: April 16, 2015
    Inventors: Ming Sun, Kai Liu, Xiao Tian Zhang, Yueh Se Ho, Leeshawn Luo
  • Patent number: 8994140
    Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Publication number: 20150087114
    Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Patent number: 8987878
    Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: March 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
  • Patent number: 8981464
    Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: March 17, 2015
    Assignee: Alpha and Omega Semiconductor Ltd
    Inventors: Tao Feng, François Hébert, Ming Sun, Yueh-Se Ho
  • Publication number: 20150056752
    Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.
    Type: Application
    Filed: November 5, 2014
    Publication date: February 26, 2015
    Inventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
  • Patent number: 8952509
    Abstract: The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Yueh-Se Ho, Yan Xun Xue, Jun Lu, Xiaotian Zhang, Zhi Qiang Niu, Ming-Chen Lu, Liang Zhao, YuPing Gong, GuoFeng Lian