Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Abstract: A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1?i?n?1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th input; a first FET and a second FET in series configured for connecting the i-th column to a defined voltage level; wherein a first gate signal renders the first FET conductive, if the i-th column is not in conductive connection with the i-th input; wherein a second gate signal renders the second FET conductive, if the i-th column is not in conductive connection with the (i+1)-th input.

Abstract: Embodiments include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

Abstract: A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

Abstract: A technique to generate timing control for an SRAM circuit operating with dual power supplies is provided. A voltage signal is generated by a programmable local clock buffer that receives power from a first voltage level. The voltage signal is shifted higher by a level shifter that receives power from both the first voltage level and a second voltage level. The voltage signal is delayed by a delay clock chopper circuit that receives power from the second voltage level. The delay clock chopper circuit includes a programmable pulse width variation (PWVAR) circuit that varies the pulse width of the voltage signal. The PWVAR circuit receives power from the second voltage level. The voltage signal drives a global bitline of the SRAM. The voltage signal has timing sensitive to both the first and second voltage levels. The voltage signal has its pulse width sensitive to the second voltage level.

Abstract: Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

Abstract: An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.

Abstract: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

Abstract: A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.

Abstract: A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.