Patents by Inventor Yuen H. Chan

Yuen H. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4851711
    Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
    Type: Grant
    Filed: February 2, 1988
    Date of Patent: July 25, 1989
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Rolf H. Nijhuis, Carlos G. Rivadeneira, James R. Struk
  • Patent number: 4752913
    Abstract: Disclosed is an improved bit selection circuit for a RAM, in particular one employing CTS (complementary transistor switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto a bit select circuit, each of the bit select circuits being connected to an output of the second level decoder, a bit up-level clamp circuit connected to each of the bit select circuits of each pair of bit lines, each of the bit select circuits including a first circuit for increasing the speed of selection of the selected pair of lines, the bit up-level clamp circuit cooperating with the bit select circuit of the selected pair of bit lines for positively limiting the upper potential level of the selected pair of bit lines, and each of the bit select circuits including a second circuit for increasing the speed of deselection of the selected pair of bit lines.
    Type: Grant
    Filed: April 30, 1986
    Date of Patent: June 21, 1988
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, James R. Struk
  • Patent number: 4598390
    Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: July 1, 1986
    Assignee: International Business Machines Corporation
    Inventor: Yuen H. Chan
  • Patent number: 4596002
    Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: June 17, 1986
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Frank D. Jones, William F. Stinson
  • Patent number: 4578779
    Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly, to improved word line selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: March 25, 1986
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, James R. Struk
  • Patent number: 4529894
    Abstract: Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node.
    Type: Grant
    Filed: June 15, 1981
    Date of Patent: July 16, 1985
    Assignee: IBM Corporation
    Inventors: Yuen H. Chan, James E. Dickerson, Walter S. Klara, Theodore W. Kwap, Joseph M. Mosley