Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.

Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.