Patents by Inventor Yuichi Hirano
Yuichi Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8912590Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.Type: GrantFiled: May 15, 2012Date of Patent: December 16, 2014Assignee: Renesas Electronics CorporationInventor: Yuichi Hirano
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Patent number: 8878301Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.Type: GrantFiled: July 19, 2011Date of Patent: November 4, 2014Assignee: Renesas Electronics CorporationInventor: Yuichi Hirano
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Publication number: 20140302646Abstract: A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first MISFET and a dummy gate electrode for a second MISFET are formed, and then, an insulating film is partially formed on the gate electrode. Then, on the semiconductor substrate, an insulating film is formed so as to cover the dummy gate electrode, the gate electrode and other insulating film. Then, the dummy gate electrode is exposed by polishing the insulating film. In this polishing, the insulating film is polished under a condition that a polishing speed of the other insulating film is smaller than a polishing speed of the insulating film. Then, after the dummy gate electrode is removed, the gate electrode for the second MISFET is formed in a region where the dummy gate electrode has been removed.Type: ApplicationFiled: April 4, 2014Publication date: October 9, 2014Applicant: Renesas Electronics CorporationInventors: Yuichi Hirano, Tatsuyoshi Mihara, Keisuke Tsukamoto
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Patent number: 8513058Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of theType: GrantFiled: February 2, 2011Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Toshiaki Iwamatsu, Yuichi Hirano
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Publication number: 20120306001Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.Type: ApplicationFiled: May 15, 2012Publication date: December 6, 2012Inventor: Yuichi HIRANO
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Publication number: 20120061767Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.Type: ApplicationFiled: July 19, 2011Publication date: March 15, 2012Inventor: Yuichi HIRANO
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Publication number: 20110269089Abstract: A heat treatment apparatus for a selenization process or a sulphurization process carried out when forming a light absorbing layer in a chalcopyrite-type solar cell, comprises a quartz tube in which a plurality of solar cell substrates is arranged in parallel at predetermined intervals in a thickness direction, a heating mechanism for heating atmospheric gas, which is arranged at an outside of the quartz tube, and first baffle plates arranged upward of the substrates, in which heated atmospheric gas, which rises along an inner surface of the quartz tube, is guided from upward to the center of the substrates.Type: ApplicationFiled: April 14, 2009Publication date: November 3, 2011Applicant: HONDA MOTOR CO., LTDInventors: Takeshi Echizenya, Yuichi Hirano, Hitoshi Nagasaki, Yoshinori Tokunaga, Satoshi Yonezawa
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Publication number: 20110186936Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of theType: ApplicationFiled: February 2, 2011Publication date: August 4, 2011Inventors: Toshiaki IWAMATSU, Yuichi Hirano
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Publication number: 20100314686Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: Renesas Technology Corp.Inventor: Yuichi HIRANO
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Patent number: 7804132Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.Type: GrantFiled: April 10, 2007Date of Patent: September 28, 2010Assignee: Renesas Technology Corp.Inventor: Yuichi Hirano
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Publication number: 20080179676Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.Type: ApplicationFiled: January 9, 2008Publication date: July 31, 2008Inventors: Yuichi HIRANO, Takashi Ipposhi, Toshiaki Iwamatsu, Yukio Maki, Mikio Tsujiuchi
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Publication number: 20070241402Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.Type: ApplicationFiled: April 10, 2007Publication date: October 18, 2007Applicant: Renesas Technology Corp.Inventor: Yuichi HIRANO
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Patent number: 6335267Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.Type: GrantFiled: September 22, 2000Date of Patent: January 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Shigenobu Maeda, Yuichi Hirano
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Patent number: 6191450Abstract: An FS upper nitride film (15) is formed on the upper surface of an FS electrode (5). Therefore, the upper surface of the FS electrode (5) is not exposed even when an FS upper oxide film (41) is partially almost removed in the manufacturing process. Thus, a semiconductor device which prevents degradation in operation characteristics and reliability due to existence of an FS insulating layer can be provided.Type: GrantFiled: December 15, 1997Date of Patent: February 20, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Toshiaki Iwamatsu, Shigeto Maegawa, Takashi Ipposhi, Yasuo Yamaguchi, Yuichi Hirano
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Patent number: 6150696Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.Type: GrantFiled: April 7, 1998Date of Patent: November 21, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Shigenobu Maeda, Yuichi Hirano