Patents by Inventor Yuichi Onozawa

Yuichi Onozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098252
    Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi ONOZAWA
  • Patent number: 10950446
    Abstract: Provided is a semiconductor device including: a semiconductor substrate doped with an impurity; a front-surface-side electrode provided at a side of a front surface of the semiconductor substrate; and a back-surface-side electrode provided at a side of a back surface of the semiconductor substrate; wherein the semiconductor substrate includes: a peak region arranged at the side of the back surface of the semiconductor substrate and having one or more peaks of an impurity concentration; a high concentration region arranged closer to the front surface than the peak region and having an impurity concentration more gently sloped than the one or more peaks; and a low concentration region arranged closer to the front surface than the high concentration region and having an impurity concentration lower than the impurity concentration of the high concentration region and a substrate concentration of the semiconductor substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa, Akio Yamano
  • Patent number: 10923570
    Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa
  • Publication number: 20210043739
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Inventors: Yoshiharu KATO, Toru AJIKI, Tohru SHIRAKAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Takashi YOSHIMURA, Yuichi ONOZAWA, Hiroshi TAKISHITA, Soichi YOSHIDA
  • Patent number: 10916628
    Abstract: Provided is a semiconductor device including a drift region having a first conductivity type provided on a semiconductor substrate; a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate; a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate; an emitter region having the first conductivity type provided above the base region, on a top surface of the mesa portion; and a contact region having the second conductivity type and a higher doping concentration than the base region, provided adjacent to the emitter region on the top surface of the mesa portion, wherein a mesa width of the mesa portion is less than or equal to 100 nm, and a bottom end of the contact region is shallower than a bottom end of the emitter region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa, Akio Nakagawa
  • Patent number: 10867790
    Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Publication number: 20200388611
    Abstract: A semiconductor device is provided that has a semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer, and an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein the accumulation region has a first accumulation region and a second accumulation region that is formed more shallowly than the first accumulation region is and on a side of a boundary with a region that is different from the accumulation region in a planar view.
    Type: Application
    Filed: August 23, 2020
    Publication date: December 10, 2020
    Inventors: Yuichi ONOZAWA, Kota OHI
  • Publication number: 20200381515
    Abstract: Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Inventors: Takahiro TAMURA, Yuichi ONOZAWA, Takashi YOSHIMURA, Hiroshi TAKISHITA, Akio YAMANO
  • Patent number: 10847609
    Abstract: A front surface element structure is formed on the front surface side of an n?-type semiconductor substrate. Then defects are formed throughout an n?-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n?-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n?-type semiconductor substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Hiroshi Takishita, Takashi Yoshimura
  • Publication number: 20200350170
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Takahiro TAMURA, Yuichi ONOZAWA, Misaki TAKAHASHI
  • Publication number: 20200335497
    Abstract: A semiconductor device includes a transistor portion which includes a plurality of gate structure portions, and a diode portion which includes a cathode region in a lower surface of a semiconductor substrate. Each of the gate structure portions includes a gate trench portion, an emitter region of a first conductive type which is provided between an upper surface of the semiconductor substrate and a drift region to abut on the gate trench portion, and a base region of a second conductive type which is provided between the emitter region and the drift region to abut on the gate trench portion. A first threshold of the gate structure portion with a shortest distance to the cathode region in a top view is lower than a second threshold of the gate structure portion with a longest distance to the cathode region by 0.1 V or more and 1 V or less.
    Type: Application
    Filed: February 18, 2020
    Publication date: October 22, 2020
    Inventors: Kaname MITSUZUKA, Tohru SHIRAKAWA, Toru AJIKI, Yuichi ONOZAWA
  • Patent number: 10770453
    Abstract: A semiconductor device is provided that has a semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer, and an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein the accumulation region has a first accumulation region and a second accumulation region that is formed more shallowly than the first accumulation region is and on a side of a boundary with a region that is different from the accumulation region in a planar view.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Kota Ohi
  • Patent number: 10756182
    Abstract: Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita, Akio Yamano
  • Patent number: 10734230
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi
  • Patent number: 10707300
    Abstract: A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa, Akio Nakagawa
  • Publication number: 20200194562
    Abstract: Provided is a semiconductor device including a semiconductor substrate; a hydrogen donor that is provide inside the semiconductor substrate in a depth direction, has a doping concentration that is higher than a doping concentration of a dopant of the semiconductor substrate, has a doping concentration distribution peak at a first position that is a predetermined distance in the depth direction of the semiconductor substrate away from one main surface of the semiconductor substrate, and has a tail of the doping concentration distribution where the doping concentration is lower than at the peak, farther on the one main surface side than where the first position is located; and a crystalline defect region having a crystalline defect density center peak at a position shallower than the first position, in the depth direction of the semiconductor substrate.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: Takashi YOSHIMURA, Yuichi ONOZAWA, Hiroshi TAKISHITA, Misaki MEGURO, Motoyoshi KUBOUCHI, Naoko KODAMA
  • Publication number: 20200161479
    Abstract: Provided is a semiconductor apparatus in which the buried region includes an end portion buried region continuously disposed from a region below the contact opening up to a region below the interlayer dielectric film while passing below an end portion of the contact opening in a cross section perpendicular to the upper surface of the semiconductor substrate, and the end portion buried region disposed below the interlayer dielectric film is shorter than the end portion buried region disposed below the contact opening in a first direction in parallel with the upper surface of the semiconductor substrate.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Takahiro TAMURA, Yuichi ONOZAWA
  • Patent number: 10651302
    Abstract: A semiconductor device including: a semiconductor substrate; a drift region of first conductivity type that is formed in the semiconductor substrate; an accumulation region of first conductivity type that is formed above the drift region and has higher concentration than concentration of the drift region; a base region of second conductivity type that is formed above the accumulation region; and a gate trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein a maximum value of doping concentration of the accumulation region is greater than a maximum value of doping concentration of the base region will be provided.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa
  • Publication number: 20200144360
    Abstract: A front surface element structure is formed on the front surface side of an n?-type semiconductor substrate. Then defects are formed throughout an n?-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n?-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n?-type semiconductor substrate.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi ONOZAWA, Hiroshi TAKISHITA, Takashi YOSHIMURA
  • Publication number: 20200098747
    Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.
    Type: Application
    Filed: November 29, 2019
    Publication date: March 26, 2020
    Inventors: Takahiro TAMURA, Yuichi ONOZAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Daisuke OZAKI, Akinori KANETAKE