Patents by Inventor Yuichi Takeuchi

Yuichi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9614071
    Abstract: A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a source layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 4, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Masahiro Sugimoto, Yuichi Takeuchi
  • Publication number: 20170086659
    Abstract: A diagnosis assisting apparatus includes a region extraction section configured to extract, from among fluorescence images obtained by picking up images of fluorescence emitted from a desired object, a reference region to be handled as a reference for a fluorescence generation state and a region of interest to be handled as a comparison target of the fluorescence generation state, respectively, a calculation processing section configured to acquire a reference value corresponding to a luminance value of each pixel included in the reference region and calculate a calculation value obtained by dividing the luminance value of the region of interest by a representative value, a storage section configured to store the calculation value calculated by the calculation processing section, and an image processing section configured to cause a display apparatus to display information indicating a variation over time of the calculation value stored in the storage section.
    Type: Application
    Filed: December 7, 2016
    Publication date: March 30, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Hiroki UCHIYAMA, Toshiaki WATANABE, Yuichi TAKEUCHI
  • Publication number: 20170092742
    Abstract: A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being. implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.
    Type: Application
    Filed: August 12, 2016
    Publication date: March 30, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru ONISHI, Atsushi ONOGI, Tadashi MISUMI, Yusuke YAMASHITA, Yuichi TAKEUCHI
  • Patent number: 9608104
    Abstract: A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift layer; a base region; a source region; a trench gate structure; a source electrode; and a drain electrode. The base region has a high-concentration base region and a low-concentration base region having a second conductivity type with an impurity concentration lower than the high-concentration base region, which are stacked each other. Each of the high-concentration base region and the low-concentration base region contacts a side surface of the trench.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: March 28, 2017
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Jun Morimoto, Narumasa Soejima
  • Publication number: 20170084735
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Yuichi TAKEUCHI, Naohiro SUZUKI, Masahiro SUGIMOTO, Hidefumi TAKAYA, Akitaka SOENO, Jun MORIMOTO, Narumasa SOEJIMA, Yukihiko WATANABE
  • Patent number: 9600211
    Abstract: An information processing apparatus includes a unit that acquires information specifying prices of pages of a to-be-printed document, a unit that receives, from a user, an input of information identifying a not-to-be-printed page of the to-be-printed document, a replacement-document-acquiring unit that acquires at least one replacement document whose total price corresponds to a total price of the not-to-be-printed page identified based on the information, a printing controller that controls to cause a printing mechanism to print a document obtained by replacing the not-to-be-printed page with the acquired replacement document, and a billing unit that charges the user a total price of the printed pages of the to-be-printed document and charges a provider of the replacement document a price of the replacement document printed as a replacement for the not-to-be-printed page.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 21, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Yuichi Takeuchi
  • Publication number: 20170060487
    Abstract: An information processing apparatus includes a unit that acquires information specifying prices of pages of a to-be-printed document, a unit that receives, from a user, an input of information identifying a not-to-be-printed page of the to-be-printed document, a replacement-document-acquiring unit that acquires at least one replacement document whose total price corresponds to a total price of the not-to-be-printed page identified based on the information, a printing controller that controls to cause a printing mechanism to print a document obtained by replacing the not-to-be-printed page with the acquired replacement document, and a billing unit that charges the user a total price of the printed pages of the to-be-printed document and charges a provider of the replacement document a price of the replacement document printed as a replacement for the not-to-be-printed page.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 2, 2017
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Yuichi TAKEUCHI
  • Publication number: 20170047394
    Abstract: In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 16, 2017
    Inventor: Yuichi TAKEUCHI
  • Publication number: 20170027508
    Abstract: A biological information detecting device includes: a biological information detector which detects biological information of a subject; and a band. In the band, a first surface which is on the side of the subject when the band is worn is wave-shaped in a cross section taken along a long-side direction of the band.
    Type: Application
    Filed: July 30, 2016
    Publication date: February 2, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tetsu NAKAYAMA, Hideto YAMASHITA, Yuichi TAKEUCHI, Yasutomo TAKAHASHI
  • Publication number: 20170020377
    Abstract: A fluorescence observation endoscope system includes a light source apparatus configured to include one light emitting body configured to be able to emit light in a first wavelength band which is radiated onto medicine administered to a living body to thereby emit fluorescence, light in a second wavelength band and light in a third wavelength band, a light guide, an image pickup section configured to include an image pickup device to simultaneously receive the fluorescence and reflected light of the light in the second and third wavelength bands, and a signal processing apparatus configured to generate color display images from an image pickup signal of the fluorescence and second and third image pickup signals acquired from the reflected light of the light in the second and third wavelength bands.
    Type: Application
    Filed: October 4, 2016
    Publication date: January 26, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Yuichi TAKEUCHI, Toshiaki WATANABE
  • Publication number: 20170012109
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Nozomu AKAGI, Jun SAKAKIBARA, Shoji MIZUNO, Yuichi TAKEUCHI
  • Publication number: 20170012108
    Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Jun SAKAKIBARA, Nozomu AKAGI, Shoji MIZUNO, Yuichi TAKEUCHI, Katsumi SUZUKI
  • Patent number: 9543428
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 10, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9515160
    Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 6, 2016
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Kazumi Chida, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9515197
    Abstract: In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: December 6, 2016
    Assignee: DENSO CORPORATION
    Inventor: Yuichi Takeuchi
  • Publication number: 20160351680
    Abstract: A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.
    Type: Application
    Filed: October 6, 2014
    Publication date: December 1, 2016
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Akitaka SOENO, Yuichi TAKEUCHI, Narumasa SOEJIMA
  • Patent number: 9450068
    Abstract: In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 20, 2016
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Naohiro Sugiyama
  • Patent number: 9412831
    Abstract: In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: August 9, 2016
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Naohiro Sugiyama
  • Publication number: 20160163818
    Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.
    Type: Application
    Filed: January 20, 2016
    Publication date: June 9, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi TAKEUCHI, Kazumi CHIDA, Narumasa SOEJIMA, Yukihiko WATANABE
  • Patent number: 9337298
    Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: May 10, 2016
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Kazumi Chida, Narumasa Soejima, Yukihiko Watanabe