Patents by Inventor Yuichiro HANYU

Yuichiro HANYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220045216
    Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Inventors: Yohei YAMAGUCHI, Yuichiro HANYU, Hiroki HIDAKA
  • Patent number: 11189734
    Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 30, 2021
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Yuichiro Hanyu, Hiroki Hidaka
  • Publication number: 20210367082
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Applicant: Japan Display Inc.
    Inventors: Takeshi SAKAI, Yuichiro HANYU, Masahiro WATABE
  • Patent number: 11114568
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 7, 2021
    Assignee: Japan Display Inc.
    Inventors: Takeshi Sakai, Yuichiro Hanyu, Masahiro Watabe
  • Publication number: 20200227563
    Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 16, 2020
    Inventors: Yohei YAMAGUCHI, Yuichiro HANYU, Hiroki HIDAKA
  • Publication number: 20200227569
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Japan Display Inc.
    Inventors: Takeshi SAKAI, Yuichiro HANYU, Masahiro WATABE
  • Patent number: 10629750
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Japan Display Inc.
    Inventors: Takeshi Sakai, Yuichiro Hanyu, Masahiro Watabe
  • Patent number: 10608016
    Abstract: A display device has a thin film transistor on a substrate. The thin film transistor includes a first transistor having an oxide semiconductor film, a first gate insulating film, and a first gate electrode and a second transistor having a silicon semiconductor film, a second gate insulating film, and a second gate electrode. The first gate insulating film includes a first insulating film and a second insulating film. The oxide semiconductor film is positioned between the first insulating film and the substrate. The first insulating film is positioned between the silicon semiconductor film and the substrate and between the second insulating film and the substrate. The second gate insulating film includes an insulating film made of the same material in the same layer as the second insulating film. The first gate electrode and the second gate electrode are in the same layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 31, 2020
    Assignee: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Arichika Ishida, Masahiro Watabe
  • Patent number: 10522567
    Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 31, 2019
    Assignee: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Hirokazu Watanabe
  • Publication number: 20190198533
    Abstract: A display device has a thin film transistor on a substrate. The thin film transistor includes a first transistor having an oxide semiconductor film, a first gate insulating film, and a first gate electrode and a second transistor having a silicon semiconductor film, a second gate insulating film, and a second gate electrode. The first gate insulating film includes a first insulating film and a second insulating film. The oxide semiconductor film is positioned between the first insulating film and the substrate. The first insulating film is positioned between the silicon semiconductor film and the substrate and between the second insulating film and the substrate. The second gate insulating film includes an insulating film made of the same material in the same layer as the second insulating film. The first gate electrode and the second gate electrode are in the same layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Applicant: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Arichika Ishida, Masahiro Watabe
  • Patent number: 10290657
    Abstract: A display device has a thin film transistor on a substrate. The thin film transistor includes a first transistor having an oxide semiconductor film, a first gate insulating film, and a first gate electrode and a second transistor having a silicon semiconductor film, a second gate insulating film, and a second gate electrode. The first gate insulating film includes a first insulating film and a second insulating film. The oxide semiconductor film is positioned between the first insulating film and the substrate. The first insulating film is positioned between the silicon semiconductor film and the substrate and between the second insulating film and the substrate. The second gate insulating film includes an insulating film made of the same material in the same layer as the second insulating film. The first gate electrode and the second gate electrode are in the same layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Arichika Ishida, Masahiro Watabe
  • Publication number: 20180331128
    Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Applicant: Japan Display Inc.
    Inventors: Yuichiro HANYU, Hirokazu WATANABE
  • Publication number: 20180308987
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 25, 2018
    Applicant: Japan Display Inc.
    Inventors: Takeshi Sakai, Yuichiro Hanyu, Masahiro Watabe
  • Patent number: 10090332
    Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 2, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Hirokazu Watanabe
  • Publication number: 20180219029
    Abstract: A display device has a thin film transistor on a substrate. The thin film transistor includes a first transistor having an oxide semiconductor film, a first gate insulating film, and a first gate electrode and a second transistor having a silicon semiconductor film, a second gate insulating film, and a second gate electrode. The first gate insulating film includes a first insulating film and a second insulating film. The oxide semiconductor film is positioned between the first insulating film and the substrate. The first insulating film is positioned between the silicon semiconductor film and the substrate and between the second insulating film and the substrate. The second gate insulating film includes an insulating film made of the same material in the same layer as the second insulating film. The first gate electrode and the second gate electrode are in the same layer.
    Type: Application
    Filed: January 11, 2018
    Publication date: August 2, 2018
    Applicant: Japan Display Inc.
    Inventors: Yuichiro Hanyu, Arichika Ishida, Masahiro Watabe
  • Publication number: 20170358610
    Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Applicant: Japan Display Inc.
    Inventors: Yuichiro HANYU, Hirokazu WATANABE