Patents by Inventor Yuichiro Ikeda

Yuichiro Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105332
    Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Koji Katayama, Takumi Mikawa, Kiyotaka Tsuji
  • Patent number: 9001557
    Abstract: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ken Kawai, Kazuhiko Shimakawa, Yoshikazu Katoh, Yuichiro Ikeda
  • Publication number: 20150046133
    Abstract: A communication simulating system includes: a communication recording device that records, into a vehicle condition database, a vehicle condition including a step, a place and a vehicle stringed together, vehicle state information that has been input as communication content between a vehicle electric equipment system and a vehicle communication apparatus in a step performed at a predetermined place; a vehicle state information acquiring device that acquires vehicle state information from the vehicle condition database in accordance with a selected vehicle condition; a storage unit that stores communication definition files specifying the respective ones of the same processes as the communication processes executed by a plurality of ECUs included in the vehicle electric equipment system; and a communication control device that communicates with a vehicle communication apparatus in accordance with the communication process and the vehicle state information.
    Type: Application
    Filed: March 8, 2013
    Publication date: February 12, 2015
    Inventors: Yosuke Morita, Katsunori Miyazawa, Yuki Harada, Yuichiro Ikeda, Akiei Satani
  • Patent number: 8942050
    Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Ryotaro Azuma, Yoshikazu Katoh, Yuichiro Ikeda
  • Publication number: 20140321196
    Abstract: In a method for writing into a variable resistance nonvolatile memory device according to one aspect of the present disclosure, a verify write operation of newly applying a voltage pulse for changing a resistance state is performed on a variable resistance element which does not satisfy a determination condition for verifying that the resistance state has been changed despite application of a voltage pulse for changing the resistance state, and the determination condition in the verify write operation is relaxed when an average number of times of verify write operation, having already been performed on all or part of a plurality of variable resistance elements that are targets for write operation, exceeds a predetermined number of times.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 30, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro IKEDA, Kazuhiko SHIMAKAWA, Yoshikazu KATOH, Ken KAWAI
  • Patent number: 8848422
    Abstract: A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Yuichiro Ikeda
  • Patent number: 8848424
    Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Patent number: 8798843
    Abstract: After a request for first data is received from a first diagnostic unit, when a request for second data is received from a second diagnostic unit, if the first data and the second data of the same type, then a communication unit requests the electronic control unit to send the same type of data, and sends the same type of data received from the electronic control unit to the first diagnostic unit and the second diagnostic unit. If the first data and the second data are of different types, then the communication unit requests the electronic control unit to send the first data and the second data, receives the first data and the second data all together from the electronic control unit, sends the received first data to the first diagnostic unit, and sends the received second data to the second diagnostic unit.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 5, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventors: Kazumori Sakai, Taku Makita, Hiroki Hashimoto, Yuichiro Ikeda, Yosuke Morita
  • Publication number: 20140126267
    Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.
    Type: Application
    Filed: March 7, 2013
    Publication date: May 8, 2014
    Applicant: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Koji Katayama, Takumi Mikawa, Kiyotaka Tsuji
  • Patent number: 8687409
    Abstract: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma, Ken Kawai
  • Publication number: 20140078811
    Abstract: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
    Type: Application
    Filed: November 21, 2012
    Publication date: March 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Ken Kawai, Kazuhiko Shimakawa, Yoshikazu Katoh, Yuichiro Ikeda
  • Patent number: 8675387
    Abstract: A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: March 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Yoshihiko Kanzawa, Shunsaku Muraoka, Yoshikazu Katoh
  • Publication number: 20140056055
    Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.
    Type: Application
    Filed: November 15, 2012
    Publication date: February 27, 2014
    Applicant: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Patent number: 8467228
    Abstract: Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 18, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Patent number: 8467229
    Abstract: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: June 18, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Publication number: 20130114327
    Abstract: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
    Type: Application
    Filed: May 30, 2012
    Publication date: May 9, 2013
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma, Ken Kawai
  • Publication number: 20130070516
    Abstract: A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.
    Type: Application
    Filed: April 19, 2012
    Publication date: March 21, 2013
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Yuichiro Ikeda
  • Publication number: 20130021838
    Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
    Type: Application
    Filed: September 7, 2011
    Publication date: January 24, 2013
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Ryotaro Azuma, Yoshikazu Katoh, Yuichiro Ikeda
  • Publication number: 20120236628
    Abstract: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
    Type: Application
    Filed: November 24, 2011
    Publication date: September 20, 2012
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Publication number: 20120176834
    Abstract: Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
    Type: Application
    Filed: August 10, 2011
    Publication date: July 12, 2012
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma