Patents by Inventor Yuichiro Ikeda

Yuichiro Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120236628
    Abstract: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
    Type: Application
    Filed: November 24, 2011
    Publication date: September 20, 2012
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Publication number: 20120176834
    Abstract: Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
    Type: Application
    Filed: August 10, 2011
    Publication date: July 12, 2012
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Publication number: 20110296684
    Abstract: This disclosure provides a method of adjusting capacities of combustion chambers of a multi-cylinder engine having a cylinder head with recessed parts that partially form the combustion chambers and a mating surface for mating with a cylinder block, which includes casting a cylinder head material having flat reference surfaces on top of the recessed parts of the cylinder head, machining the cylinder head material to form the mating surface, measuring distances in a height direction from the mating surface to the reference surfaces, respectively, and adjusting machining margins of machining portions of the reference surfaces of the recessed parts based on the measured height direction distances.
    Type: Application
    Filed: May 3, 2011
    Publication date: December 8, 2011
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Tsuyoshi Yamamoto, Yasushi Nakahara, Takayuki Yamada, Kazuya Hayashi, Yuichiro Ikeda
  • Publication number: 20110182109
    Abstract: A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
    Type: Application
    Filed: July 26, 2010
    Publication date: July 28, 2011
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Yoshihiko Kanzawa, Shunsaku Muraoka, Yoshikazu Katoh
  • Publication number: 20110118933
    Abstract: After a request for first data is received from a first diagnostic unit, when a request for second data is received from a second diagnostic unit, if the first data and the second data of the same type, then a communication unit requests the electronic control unit to send the same type of data, and sends the same type of data received from the electronic control unit to the first diagnostic unit and the second diagnostic unit. If the first data and the second data are of different types, then the communication unit requests the electronic control unit to send the first data and the second data, receives the first data and the second data all together from the electronic control unit, sends the received first data to the first diagnostic unit, and sends the received second data to the second diagnostic unit.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 19, 2011
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Kazumori Sakai, Taku Makita, Hiroki Hashimoto, Yuichiro Ikeda, Yosuke Morita
  • Patent number: 7375958
    Abstract: A plurality of specific external connecting parts can be short-circuited, without increasing the number of parts and mounting work. A plurality of external connecting parts provided in parallel to each other, and a short-circuit part for short-circuiting edges located at rear end side of each of a first external connecting part and a second external connecting part which separate external connecting parts not short-circuited among the external connecting parts are inserted therebetween are comprised. The short-circuit part is formed by upward or downward bending process, and has a curved part.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: May 20, 2008
    Assignee: Alps Electric Co., Ltd.
    Inventors: Yoshimasa Kuroda, Yuichiro Ikeda
  • Patent number: 7239572
    Abstract: This multiport memory has a memory hold circuit, a plurality of write circuits and read circuits, and a read/write capability regulating circuit. The read/write capability regulating circuit individually sets a write/read capability of each of the write/read circuits. The read/write capability regulating circuit determines, using an operating state determining circuit, the number of writing/reading times per unit time in accordance with an operating state of each of the read/write circuits. As the operating state determining circuit used is a noise amount detection circuit, an operation completion detecting circuit, or a potential fluctuation detecting circuit.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: July 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichiro Ikeda
  • Patent number: 7021085
    Abstract: The multi-colored fiber pile fabric of the present invention has at least one cut pile layer comprising a plurality of cut piles extending from at least one surface side of a knit or weave structure formed from organic fiber yarns, the cut pile layer comprises non-crimped pile fibers 5 formed from non-crimped organic fibers, crimped pile fibers 6 formed from crimped organic fibers and having a pile height lower than that of the non-crimped pile fibers 5 and crimped or non-crimped pile fibers 7 formed from crimped or non-crimped organic fibers and having a pile height lower than that of the crimped pile fibers 6, at least one type of pile fibers of the piles fibers 5, 6 and 7 having a color different in lightness or hue or lightness and hue from the other(s),
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: April 4, 2006
    Assignee: Teijin Fibers Limited
    Inventors: Yuichiro Ikeda, Takuya Tamura
  • Publication number: 20060023557
    Abstract: This multiport memory has a memory hold circuit, a plurality of write circuits and read circuits, and a read/write capability regulating circuit. The read/write capability regulating circuit individually sets a write/read capability of each of the write/read circuits. The read/write capability regulating circuit determines, using an operating state determining circuit, the number of writing/reading times per unit time in accordance with an operating state of each of the read/write circuits. As the operating state determining circuit used is a noise amount detection circuit, an operation completion detecting circuit, or a potential fluctuation detecting circuit.
    Type: Application
    Filed: July 20, 2005
    Publication date: February 2, 2006
    Inventor: Yuichiro Ikeda
  • Patent number: 6979227
    Abstract: According to the present invention, there is provided a card adapter which is capable of preventing contact failure between a cover member and a ground terminal caused by the floating of the cover member when a card is inserted into a card inserting portion. A contacting surface 40 facing a back-end surface 1b of the card inserting portion 1a is provided on the ground terminal 12. A ground contacting portion 41 comprising a contacting portion 41a brought into contact with the contacting surface 40, a plate spring portion 41b extending in a widthwise direction of the card inserting portion 1a and bent in a lengthwise direction of the card inserting portion 1a, and a cantilever supporting portion 41c for supporting the plate spring portion 41b in a cantilever manner is formed in a bent portion 4a provided in a front-end portion of the cover member 4.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: December 27, 2005
    Assignee: ALPS Electric Co., Ltd.
    Inventor: Yuichiro Ikeda
  • Publication number: 20050185371
    Abstract: A plurality of specific external connecting parts can be short-circuited, without increasing the number of parts and mounting work. A plurality of external connecting parts provided in parallel to each other, and a short-circuit part for short-circuiting edges located at rear end side of each of a first external connecting part and a second external connecting part which separate external connecting parts not short-circuited among the external connecting parts are inserted therebetween are comprised. The short-circuit part is formed by upward or downward bending process, and has a curved part.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 25, 2005
    Inventors: Yoshimasa Kuroda, Yuichiro Ikeda
  • Publication number: 20050160770
    Abstract: The multi-colored fiber pile fabric of the present invention has at least one cut pile layer comprising a plurality of cut piles extending from at least one surface side of a knit or weave structure formed from organic fiber yarns, the cut pile layer comprises non-crimped pile fibers 5 formed from non-crimped organic fibers, crimped pile fibers 6 formed from crimped organic fibers and having a pile height lower than that of the non-crimped pile fibers 5 and crimped or non-crimped pile fibers 7 formed from crimped or non-crimped organic fibers and having a pile height lower than that of the crimped pile fibers 6, at least one type of pile fibers of the piles fibers 5, 6 and 7 having a color different in lightness or hue or lightness and hue from the other(s),
    Type: Application
    Filed: September 19, 2003
    Publication date: July 28, 2005
    Inventors: Yuichiro Ikeda, Takuya Tamura
  • Publication number: 20050070165
    Abstract: According to the present invention, there is provided a card adapter which is capable of preventing contact failure between a cover member and a ground terminal caused by the floating of the cover member when a card is inserted into a card inserting portion. A contacting surface 40 facing a back-end surface 1b of the card inserting portion 1a is provided on the ground terminal 12. A ground contacting portion 41 comprising a contacting portion 41a brought into contact with the contacting surface 40, a plate spring portion 41b extending in a widthwise direction of the card inserting portion 1a and bent in a lengthwise direction of the card inserting portion 1a, and a cantilever supporting portion 41c for supporting the plate spring portion 41b in a cantilever manner is formed in a bent portion 4a provided in a front-end portion of the cover member 4.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 31, 2005
    Inventor: Yuichiro Ikeda
  • Patent number: 5319321
    Abstract: A digital PLL circuit capable of stabilizing a phase comparison operation to largely reduce a jitter of an output signal, including a peak detection circuit for detecting a peak of an input signal level, a two-points sampling circuit for sampling two data points determined at a predetermined time interval in the peak to output two sample values, an inclination calculation circuit for calculating an inclination value from the two sample values, and a discrimination circuit for discriminating whether the inclination value is zero or either a positive or negative value to output a control signal for a VCO depending on the discrimination result.
    Type: Grant
    Filed: February 2, 1993
    Date of Patent: June 7, 1994
    Assignee: NEC Corporation
    Inventor: Yuichiro Ikeda