Patents by Inventor Yuji KARAKANE

Yuji KARAKANE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200185373
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10409338
    Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Manabu Matsumoto, Katsuya Murakami, Akira Tanimoto, Isao Ozawa, Yuji Karakane, Tadashi Shimazaki
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Publication number: 20180076187
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 15, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Publication number: 20170010639
    Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.
    Type: Application
    Filed: March 1, 2016
    Publication date: January 12, 2017
    Inventors: Manabu MATSUMOTO, Katsuya MURAKAMI, Akira TANIMOTO, Isao OZAWA, Yuji KARAKANE, Tadashi SHIMAZAKI
  • Patent number: 9209053
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Goto, Takashi Imoto, Takeshi Watanabe, Yuusuke Takano, Yusuke Akada, Yuji Karakane, Yoshinori Okayama, Akihiko Yanagida
  • Publication number: 20150171060
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.
    Type: Application
    Filed: September 10, 2014
    Publication date: June 18, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki GOTO, Takashi IMOTO, Takeshi WATANABE, Yuusuke TAKANO, Yusuke AKADA, Yuji KARAKANE, Yoshinori OKAYAMA, Akihiko YANAGIDA
  • Publication number: 20150171056
    Abstract: In a manufacturing method of a semiconductor device of an embodiment, a plurality of semiconductor packages, as objects to be processed, each including a semiconductor chip mounted on a wiring board and a sealing resin layer, and a tray including a plurality of housing parts are prepared. The semiconductor packages are respectively disposed in the plurality of housing parts of the tray. A metal material is sputtered on the semiconductor packages disposed in the housing parts, to thereby form a conductive shield layer covering an upper surface and side surfaces of each of the sealing resin layers and at least a part of side surfaces of each of the wiring boards.
    Type: Application
    Filed: September 10, 2014
    Publication date: June 18, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Goto, Takashi Imoto, Takeshi Watanabe, Yuusuke Takano, Yusuke Akada, Yuji Karakane, Yoshinori Okayama, Akihiko Yanagida
  • Publication number: 20120286411
    Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.
    Type: Application
    Filed: March 16, 2012
    Publication date: November 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato
  • Publication number: 20120153471
    Abstract: A semiconductor device according to the present embodiment includes a substrate including wirings. At least one first semiconductor chip is mounted on a first surface of the substrate and is electrically connected to any of the wirings. A first metal ball is provided on the first surface of the substrate and is electrically connected to the first semiconductor chip through any of the wirings. A first resin seals the wirings, the first semiconductor chip, and the first metal ball on the first surface of the substrate. A top of the first metal ball protrudes from a surface of the first resin and is exposed.
    Type: Application
    Filed: September 18, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi WATANABE, Yuji Karakane, Takashi Imoto
  • Publication number: 20120153432
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a control element provided on the substrate, a resin provided on the control element and a memory element provided above the control element. The memory element is in contact with the resin and electrically connected to the control element provided within a region therebeneath in plan view parallel to a surface of the substrate.
    Type: Application
    Filed: September 15, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuji KARAKANE, Yoriyasu ANDO