Patents by Inventor Yuji Tsukada
Yuji Tsukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7880256Abstract: The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing.Type: GrantFiled: March 22, 2006Date of Patent: February 1, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Takai, Takuya Suzuki, Yuji Tsukada
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Patent number: 7419874Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.Type: GrantFiled: January 12, 2006Date of Patent: September 2, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Tatsuya Fujishima, Mikio Fukuda, Yuji Tsukada, Keiji Ogata, Izuo Iida
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Publication number: 20060249845Abstract: The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing.Type: ApplicationFiled: March 22, 2006Publication date: November 9, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Nobuyuki Takai, Takuya Suzuki, Yuji Tsukada
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Publication number: 20060172488Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.Type: ApplicationFiled: January 12, 2006Publication date: August 3, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tatsuya Fujishima, Mikio Fukuda, Yuji Tsukada, Keiji Ogata, Izuo Iida
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Publication number: 20060008962Abstract: The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and a SiO2 film in a second region is removed by etching. After the photoresist layer is removed, a silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a first gate insulation film in the second region. Then, the SiO2 film in the third region is removed by etching. After a photoresist layer is removed, the silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a second gate insulation film in the third region.Type: ApplicationFiled: July 6, 2005Publication date: January 12, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Kazuyuki Ozeki, Yuji Tsukada
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Publication number: 20050224794Abstract: The invention provides a method of forming an electrode or wiring which prevents reattachment of an etching residue in following processes by removing the etching residue at a bevel portion of a semiconductor wafer. An insulation film is formed so as to cover a front surface and a back surface of a semiconductor wafer, and then a conductive film is formed on a whole surface of the insulation film. Next, a photoresist layer is selectively formed on the conductive film by an exposure and development process. The conductive film is then selectively removed by an isotropic etching with using this photoresist layer as a mask, thereby forming an electrode or wiring of a semiconductor device. Since the electrode or the wiring of the semiconductor device is formed by isotropically etching the conductive film, a hangnail-like etching residue causing dust does not occur at the bevel portion of the wafer even though the conductive film remains on the back side of the semiconductor wafer.Type: ApplicationFiled: March 24, 2005Publication date: October 13, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Naoaki Tanaka, Yuji Tsukada, Yuichi Watanabe
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Patent number: 6614075Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.Type: GrantFiled: May 10, 2001Date of Patent: September 2, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
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Publication number: 20010025987Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N−layer 22A) and deep in the vicinity of the drain region 5 (second N−layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.Type: ApplicationFiled: May 10, 2001Publication date: October 4, 2001Applicant: Sanyo Electric Co., Ltd., a Japan CorporationInventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
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Patent number: 6255154Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.Type: GrantFiled: February 24, 2000Date of Patent: July 3, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
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Patent number: D821210Type: GrantFiled: June 2, 2017Date of Patent: June 26, 2018Assignee: JXTG NIPPON OIL & ENERGY CORPORATIONInventor: Yuji Tsukada
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Patent number: D828167Type: GrantFiled: June 2, 2017Date of Patent: September 11, 2018Assignee: JXTG NIPPON OIL & ENERGY CORPORATIONInventor: Yuji Tsukada