Patents by Inventor Yuki Kondoh

Yuki Kondoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10983924
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 20, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Publication number: 20190251041
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventor: Yuki KONDOH
  • Patent number: 10289569
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Publication number: 20190065946
    Abstract: An activation state decision unit includes a plurality of parameter units made to process data on the basis of parameters respectively managed thereby. Each of the parameter units includes a number generator that generates a numerical number a sign of which varies, a number processor (such as an adder) that creates a parameter to process the data on the basis of the parameter and the numerical number generated by the number generator, and a parameter updating unit that updates the parameter on the basis of a cost value, which is acquired by evaluation of the processed data by an evaluation system, and the numerical number generated by the number generator. The number generator changes the generated numerical number in each data processing, and generates the numerical number in such a manner that order of a sign variation of the numerical number varies between the parameter units.
    Type: Application
    Filed: May 15, 2018
    Publication date: February 28, 2019
    Inventors: Katsuto SATO, Yuki KONDOH, Hiroaki AKUTSU
  • Patent number: 10162530
    Abstract: A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Katsuto Sato, Yuki Kondoh
  • Publication number: 20180046587
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventor: Yuki KONDOH
  • Patent number: 9798679
    Abstract: A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: October 24, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Publication number: 20170090756
    Abstract: A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 30, 2017
    Inventors: Katsuto SATO, Yuki KONDOH
  • Patent number: 9189418
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Publication number: 20150127872
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Inventors: Yuki KONDOH, Isao OHARA
  • Publication number: 20150095616
    Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventors: Hiroaki Nakaya, Yuki Kondoh, Makoto Ishikawa
  • Patent number: 8959302
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8924689
    Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Nakaya, Yuki Kondoh, Makoto Ishikawa
  • Publication number: 20140351360
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Yuki KONDOH, Isao OHARA
  • Patent number: 8868865
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8838922
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8813070
    Abstract: This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Nojiri, Yuki Kondoh
  • Patent number: 8713563
    Abstract: A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (101), each running an application program under controls of different operating systems, and a virtual machine manager (190) for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (140, 150, 151); and a resource access management module (110) for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Kondoh, Takashi Matsumoto, Keisuke Toyama, Toru Nojiri
  • Patent number: 8706996
    Abstract: The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Kondoh, Tohru Nojiri
  • Publication number: 20110131577
    Abstract: This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 2, 2011
    Inventors: Tohru NOJIRI, Yuki Kondoh