Patents by Inventor Yukifumi Oyama

Yukifumi Oyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296223
    Abstract: A wiring board includes a first wiring layer, a high-speed wiring disposed in the first wiring layer, a second wiring layer, and a signal wiring disposed in the second wiring layer. The signal wiring transmits a signal slower than that through the high-speed wiring. A third wiring layer between the first and second wiring layers includes a power supply wiring and/or a ground wiring, which is not disposed in a portion where a land of the first wiring layer and the signal wiring do not overlap. The power supply wiring and/or the ground wiring overlap the signal wiring in a portion where the land of the first wiring layer and the signal wiring overlap each other.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Yukifumi Oyama, Mitsumasa Nakamura, Yuichi Sano
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200185373
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 10607964
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Yukifumi Oyama, Keisuke Taniguchi
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Publication number: 20180076187
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 15, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 9570414
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Yukifumi Oyama, Shinya Fukayama
  • Publication number: 20160351541
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Application
    Filed: March 4, 2016
    Publication date: December 1, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Keisuke TANIGUCHI
  • Patent number: 9448065
    Abstract: A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Fukayama, Yukifumi Oyama, Kazuhiro Murakami
  • Publication number: 20160111317
    Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Satoshi TSUKIYAMA, Masatoshi FUKUDA
  • Publication number: 20160079102
    Abstract: A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Kazuhiro MURAKAMI
  • Publication number: 20150123270
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Application
    Filed: September 2, 2014
    Publication date: May 7, 2015
    Inventors: Satoshi TSUKIYAMA, Masatoshi FUKUDA, Yukifumi OYAMA, Shinya FUKAYAMA
  • Publication number: 20150069110
    Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.
    Type: Application
    Filed: February 24, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Satoshi TSUKIYAMA, Masatoshi FUKUDA
  • Publication number: 20150069634
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: March 2, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukifumi OYAMA, Hideko MUKAIDA, Masatoshi FUKUDA, Satoshi TSUKIYAMA, Shinya FUKAYAMA
  • Patent number: 7682936
    Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshihiko Nishio, Yasumitsu Orii, Yukifumi Oyama
  • Patent number: 7674651
    Abstract: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are arranged, preparing the circuit substrate having a surface thereof provided with connecting pads corresponding to respective ones of the plurality of stud-bumps, attaching the corresponding solid-solders on the solder substrate to respective tip ends of the plurality of stud bumps, separating the solid-solders attached to the tip ends of the stud-bumps from the solder substrate, contacting the solid-solder attached to respective ones of the tip ends of the stud-bumps with the corresponding connecting pads, and heating the solid-solders contacted with the corresponding connecting pads thereby establishing solder connection between respective ones of the stud-bumps and the corres
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yukifumi Oyama, Hidetoshi Nishiwaki, Toshihiko Nishio, Kazushige Toriyama, Yasumitsu Orii
  • Publication number: 20080150135
    Abstract: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are arranged, preparing the circuit substrate having a surface thereof provided with connecting pads corresponding to respective ones of the plurality of stud-bumps, attaching the corresponding solid-solders on the solder substrate to respective tip ends of the plurality of stud bumps, separating the solid-solders attached to the tip ends of the stud-bumps from the solder substrate, contacting the solid-solder attached to respective ones of the tip ends of the stud-bumps with the corresponding connecting pads, and heating the solid-solders contacted with the corresponding connecting pads thereby establishing solder connection between respective ones of the stud-bumps and the corres
    Type: Application
    Filed: September 6, 2007
    Publication date: June 26, 2008
    Inventors: Yukifumi Oyama, Hidetoshi Nishiwaki, Toshihiko Nishio, Kazushige Toriyama, Yasumitsu Orii
  • Publication number: 20080067653
    Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Nishio, Yasumitsu Orii, Yukifumi Oyama