Patents by Inventor Yukiharu Uraoka
Yukiharu Uraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220267639Abstract: [Problem] To provide a gate insulating film forming composition comprising a polysiloxane, which forms a gate insulating film having excellent characteristics such as high dielectric constant and high mobility. [Means for Solution] The gate insulating film forming composition comprises (I) a polysiloxane, (II) barium titanate, and (III) a solvent, wherein the content of the barium titanate is 30 to 80 mass % based on the total mass of the polysiloxane and the barium titanate.Type: ApplicationFiled: June 25, 2020Publication date: August 25, 2022Inventors: Yukiharu URAOKA, Juan Paolo Soria BERMUNDO, Naofumi YOSHIDA, Megumi YANO, Atsuko NOYA, Toshiaki NONAKA
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Patent number: 10916661Abstract: The present invention relates to providing a thin film transistor substrate containing a protective film, which can impart high driving stability. The thin film transistor substrate contains a thin film transistor and a protective film containing a cured product of a siloxane composition which covers the thin film transistor, wherein the thin film transistor has a semiconductor layer made of an oxide semiconductor, and wherein the siloxane composition contains polysiloxane, a fluorine-containing compound, and a solvent.Type: GrantFiled: November 27, 2017Date of Patent: February 9, 2021Assignee: Merck Patent GmbHInventors: Yukiharu Uraoka, Yasuaki Ishikawa, Naofumi Yoshida, Katsuto Taniguchi, Toshiaki Nonaka
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Patent number: 10475934Abstract: A thin film transistor having a high operation speed with a field effect mobility greater than 20 cm2/Vs and a method for manufacturing the same, and a semiconductor device having the same are provided. A thin film transistor in which a gate electrode, a gate insulating film and an oxide semiconductor film are laminated on a substrate, a source region and a drain region are respectively formed in outer portions of the oxide semiconductor film in the width direction, and a channel region is formed in a region between the source region and the drain region; and a source electrode is connected to the source region, while a drain electrode is connected to the drain region. The gate insulating film contains fluorine; and the ratio of the width W of the channel region to the length L thereof, namely W/L is less than 8.Type: GrantFiled: December 7, 2016Date of Patent: November 12, 2019Assignees: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, NISSIN ELECTRIC CO., LTD.Inventors: Yukiharu Uraoka, Haruka Yamazaki, Mami Fujii, Eiji Takahashi
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Publication number: 20190319131Abstract: [Problem] To provide a thin film transistor substrate comprising a protective film, which can impart high driving stability. [Means for Solution] A thin film transistor substrate comprising a thin film transistor and a protective film comprising a cured product of a siloxane composition, covering said thin film transistor, wherein the thin film transistor has a semiconductor layer made of an oxide semiconductor, and wherein the siloxane composition comprises polysiloxane, a fluorine-containing compound, and a solvent.Type: ApplicationFiled: November 27, 2017Publication date: October 17, 2019Inventors: Yukiharu URAOKA, Yasuaki ISHIKAWA, Naofumi YOSHIDA, Katsuto TANIGUCHI, Toshiaki NONAKA
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Publication number: 20190006525Abstract: A thin film transistor having a high operation speed with a field effect mobility greater than 20 cm2/Vs and a method for manufacturing the same, and a semiconductor device having the same are provided. A thin film transistor in which a gate electrode, a gate insulating film and an oxide semiconductor film are laminated on a substrate, a source region and a drain region are respectively formed in outer portions of the oxide semiconductor film in the width direction, and a channel region is formed in a region between the source region and the drain region; and a source electrode is connected to the source region, while a drain electrode is connected to the drain region. The gate insulating film contains fluorine; and the ratio of the width W of the channel region to the length L thereof, namely W/L is less than 8.Type: ApplicationFiled: December 7, 2016Publication date: January 3, 2019Applicants: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, NISSIN ELECTRIC CO., LTD.Inventors: Yukiharu URAOKA, Haruka YAMAZAKI, Mami FUJII, Eiji TAKAHASHI
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Patent number: 9187570Abstract: The present invention provides means useful for making devices, materials and the like that are excellent in photocatalytic activity, electric property or the like. Specifically, the present invention provides a fusion protein comprising a polypeptide portion capable of forming a multimer having an internal cavity, and a first peptide portion capable of binding to a first target substance and a second peptide portion capable of binding to a second target substance; a multimer of the fusion protein; a complex comprising the multimer of the fusion protein; and the like.Type: GrantFiled: June 21, 2013Date of Patent: November 17, 2015Assignee: Ajinomoto Co., Ltd.Inventors: Ippei Inoue, Ichiro Yamashita, Bin Zheng, Hisashi Yasueda, Yukiharu Uraoka, Yasuaki Ishikawa
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Publication number: 20140150855Abstract: A functional material having excellent photocatalytic activity, electric characteristics and the like is provided. A porous structure body 10 comprises a first target material 20 and an aggregate body 30 formed by aggregation of the first material. The aggregate body 30 adheres to the first target material and is located so as to surround the first target material. The aggregate body has a plurality of first pores 32 unevenly distributed near the first target material in the aggregate body and a plurality of second pores 34 scattered over the aggregate body.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: AJINOMOTO CO., INC.Inventors: Ippei INOUE, Ichiro Yamashita, Bin Zheng, Hisashi Yasueda, Yukiharu Uraoka, Yasuaki Ishikawa
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Publication number: 20140045247Abstract: The present invention provides means useful for making devices, materials and the like that are excellent in photocatalytic activity, electric property or the like. Specifically, the present invention provides a fusion protein comprising a polypeptide portion capable of forming a multimer having an internal cavity, and a first peptide portion capable of binding to a first target substance and a second peptide portion capable of binding to a second target substance; a multimer of the fusion protein; a complex comprising the multimer of the fusion protein; and the like.Type: ApplicationFiled: October 16, 2013Publication date: February 13, 2014Applicant: AJINOMOTO CO., INC.Inventors: IPPEI INOUE, ICHIRO YAMASHITA, BIN ZHENG, HISASHI YASUEDA, YUKIHARU URAOKA, YASUAKI ISHIKAWA
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Publication number: 20120267258Abstract: In order to provide a method for electrochemically detecting an analyte which can detect an analyte with high detection sensitivity, when detecting an analyte S trapped on a working electrode, a label binding substance 90 in which a labeling substance 93 and a first binding substance 92 which traps the analyte S are at least retained on a support 91 composed of polypeptide is brought into contact with the analyte. Alternatively, a complex containing the analyte S and a label binding substance 290 in which a labeling substance 293 is retained on a binding substance 291 which binds to the analyte S via a modulator 292 is formed. Then, the labeling substance present on the working electrode is electrochemically detected.Type: ApplicationFiled: April 20, 2012Publication date: October 25, 2012Applicants: NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, SYSMEX CORPORATIONInventors: Yukiharu URAOKA, Bin Zheng, Seigo SUZUKI, Hiroya KIRIMURA, Masayoshi SEIKE, Shigeki IWANAGA, Nobuyasu HORI
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Patent number: 7901978Abstract: The core metal of a protein such as ferritin is used as a nucleus for crystallizing a silicone thin film and then the thus crystallized film is employed in the channel part of a thin-film transistor. By aligning the protein on the surface of amorphous silicone and heating, the crystallinity is controlled. In the case of ferritin, the core diameter of the protein is 7 mm. That is, this protein is highly even in size (i.e., the metal content). Thus, the amount of the protein to be deposited on the amorphous silicone surface can be accurately controlled by controlling the protein core density. Furthermore, the type of the core metal can be altered by chemical reactions and the above method is applicable not only to amorphous silicone but also to amorphous films of various types such as germanium. Thus, the amount of nickel required in crystallization is controlled by using a protein. Moreover, the distribution density of the nickel core is controlled to thereby conduct crystallization at a desired crystal size.Type: GrantFiled: March 28, 2006Date of Patent: March 8, 2011Assignee: National University Corporation Nara Institute of Science and TechnologyInventors: Yukiharu Uraoka, Takashi Fuyuki, Hiroya Kirimura
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Publication number: 20090050880Abstract: The core metal of a protein such as ferritin is used as a nucleus for crystallizing a silicone thin film and then the thus crystallized film is employed in the channel part of a thin-film transistor. By aligning the protein on the surface of amorphous silicone and heating, the crystallinity is controlled. In the case of ferritin, the core diameter of the protein is 7 mm. That is, this protein is highly even in size (i.e., the metal content). Thus, the amount of the protein to be deposited on the amorphous silicone surface can be accurately controlled by controlling the protein core density. Furthermore, the type of the core metal can be altered by chemical reactions and the above method is applicable not only to amorphous silicone but also to amorphous films of various types such as germanium. Thus, the amount of nickel required in crystallization is controlled by using a protein. Moreover, the distribution density of the nickel core is controlled to thereby conduct crystallization at a desired crystal size.Type: ApplicationFiled: March 28, 2006Publication date: February 26, 2009Applicant: National University Corporation Nara Institute of Science and TechnologyInventors: Yukiharu Uraoka, Takashi Fuyuki, Hiroya Kirimura
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Patent number: 6323663Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.Type: GrantFiled: September 16, 1999Date of Patent: November 27, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
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Patent number: 6005401Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.Type: GrantFiled: April 14, 1997Date of Patent: December 21, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
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Patent number: 5945834Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.Type: GrantFiled: February 29, 1996Date of Patent: August 31, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
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Patent number: 5650336Abstract: A plurality of different constant currents are implanted into an element of a semiconductor device such as a gate oxide film and a metal wire, a charge-to-breakdown (or a breakdown time) is measured from a result of current implantation, a relationship between a constant current value and the charge-to-breakdown (or a breakdown time) is determined, and a time-sequence change in the current during application of a constant voltage is presumed. Next, of a time-sequence change characteristic of the current during application of the constant voltage, current values during the respective minute periods are approximated to a constant current value. Consumption ratios of the life time due to the respective current values are calculated based on a relationship between the constant current value and the charge-to-breakdown (or a breakdown time).Type: GrantFiled: September 18, 1995Date of Patent: July 22, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Yukiharu Uraoka
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Patent number: 5598100Abstract: A luminescence amount detecting part detects a weak optical radiation which a transistor in a semiconductor integrated circuit emits owing to a hot carrier effect. An output thereof is image-processed by an image processing part. An information storage part stores information on a transistor width and information on a switching frequency at an execution of a test pattern into each transistor. A switching time calculating part evaluates a switching time of the transistor from respective outputs of the image processing part and the information storage part to output a result. Thus the switching time can be evaluated easily without a electron beam tester whose operation is complicated. A delay time can be evaluated by detecting a luminescence amount which changes depending on a gate voltage, instead of measuring a gate voltage.Type: GrantFiled: November 1, 1995Date of Patent: January 28, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshinori Maeda, Yukiharu Uraoka
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Patent number: 5504431Abstract: A luminescence amount detecting part detects a weak optical radiation which a transistor in a semiconductor integrated circuit emits owing to a hot carrier effect. An output thereof is image-processed by an image processing part. An information storage part stores information on a transistor width and information on a switching frequency at an execution of a test pattern into each transistor. A switching time calculating part evaluates a switching time of the transistor from respective outputs of the image processing part and the information storage part to output a result. Thus the switching time can be evaluated easily without a electron beam tester whose operation is complicated. A delay time can be evaluated by detecting a luminescence amount which changes depending on a gate voltage, instead of measuring a gate voltage.Type: GrantFiled: December 4, 1992Date of Patent: April 2, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshinori Maeda, Yukiharu Uraoka