Patents by Inventor Yukihiro Satou

Yukihiro Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490486
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 26, 2019
    Assignees: Renesas Electronics Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Publication number: 20190027427
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 10115658
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 30, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Publication number: 20180090463
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 29, 2018
    Inventors: Yukihiro SATOU, Toshiyuki HATA
  • Patent number: 9824996
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Publication number: 20170033033
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 9496204
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 15, 2016
    Assignees: RENESAS ELECTRONICS CORPORATION, RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 9412701
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 9, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Publication number: 20150380378
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yukihiro SATOU, Toshiyuki HATA
  • Patent number: 9165901
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Patent number: 9129946
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 8, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Publication number: 20140332866
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 13, 2014
    Inventors: Yukihiro SATOU, Toshiyuki HATA
  • Publication number: 20140312510
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Inventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
  • Patent number: 8796838
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Patent number: 8796827
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Patent number: 8698289
    Abstract: The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
  • Publication number: 20140084440
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicants: HITACHI HOKKAI SEMICONDUCTOR LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Publication number: 20140003002
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 2, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
  • Patent number: 8618642
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 31, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 8581396
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 12, 2013
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou